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2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)最新文献

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Auger method to characterize metal oxides on titanium tungsten barrier layer for copper pad 用螺旋钻法表征铜垫用钛钨阻挡层上的金属氧化物
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-01 DOI: 10.1109/IPFA.2016.7564330
Wan Tatt Wai, Yong Foo Khong, Zakaria Nurhanani, Faiss Simon
{"title":"Auger method to characterize metal oxides on titanium tungsten barrier layer for copper pad","authors":"Wan Tatt Wai, Yong Foo Khong, Zakaria Nurhanani, Faiss Simon","doi":"10.1109/IPFA.2016.7564330","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564330","url":null,"abstract":"Titanium-tungsten (TiW) barrier layers were treated with process chemicals like palladium sulfate (PdSO4), diluted hydrofluoric acid (DHF), O2 plasma etc and the metal oxides change post treatments were investigated. The changes of metal oxides on surface and inside the TiW layer were characterized with Auger surface scan and depth profiling. The dominant species were identified as tungsten oxide (W-O) and copper oxide (Cu-O). Qualitative chart featuring atomic peak intensity (%) in response to the thickness (min) were plotted to show the trends of both W-O and Cu-O across the samples treated with different conditions. DHF can etch away Cu-O but at the same time enhanced W-O. Cu-O was enhanced under slow wet/dried condition at ambient air and by O2 plasma while W-O is not affected in both conditions.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115078169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of thickness on microstructure and texture in Cu thin films for interconnects 厚度对互连用Cu薄膜微观结构和织构的影响
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-01 DOI: 10.1109/IPFA.2016.7564300
L. Chen
{"title":"Effect of thickness on microstructure and texture in Cu thin films for interconnects","authors":"L. Chen","doi":"10.1109/IPFA.2016.7564300","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564300","url":null,"abstract":"Cu thin films are an attractive material for interconnects in future integrated circuits technologies. Due to their influence on the mechanical properties, microstructure and texture of thin film have become important topics in materials science. The effect of thickness on microstructure and texture in Cu thin films was investigated with EBSD (electron backscatter diffraction) and XRD (X-ray diffraction) techniques in the present work. The experimental results show that the average grain size is less than 250 nm and grain growth with the thickness increasing in Cu thin films. The volume fractions of both high-angle boundaries and Σ3 twin boundaries increase with the thickness increasing of Cu thin films. There exist stronger {111} fiber texture which has a decreased tendency with the thickness increasing of Cu thin films. It reveals the competition between the strain energy and surface/interface energy exist in Cu thin films. The microstructure and texture evolution with the thickness of Cu thin films was discussed with the theory of strain energy and surface/interface energy.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123412192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A study on device robustness with integrated effects from low parts-per-billion level of metallic elements in wafer cleaning process chemicals 晶圆清洗工艺化学品中低十亿分之一金属元素含量对器件稳健性综合影响的研究
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-01 DOI: 10.1109/IPFA.2016.7564295
K. Tan, P. L. E. Liew, C. C. Chin, C. Y. Wong
{"title":"A study on device robustness with integrated effects from low parts-per-billion level of metallic elements in wafer cleaning process chemicals","authors":"K. Tan, P. L. E. Liew, C. C. Chin, C. Y. Wong","doi":"10.1109/IPFA.2016.7564295","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564295","url":null,"abstract":"The existence of metallic elements in incoming chemicals is one of the great concerns in fab processing, degrading the fabricated device properties. In particular, with the unknown handling activity and environment influence caused by different means of transportation on the incoming chemicals stored typically in drum packaging, tight specifications in terms of various metallic species need to be enforced. These metallic impurities, if not controlled, are then introduced to the device during wafer fabrication especially during wafer cleaning process steps, with the contaminated incoming chemicals. Even trace amounts in metal concentration may alter the device electrical properties at their operating condition or even cause significant degradation over time. The impacts are especially critical on dielectric (gate oxide) quality. Correlation of such impact on device with respect to the metallic concentration level can help in setting references for reasonable specification limits, while not jeopardizing the device characteristics as well as its reliability. In this experiment, contamination levels of 0.1, 0.4, 0.7 and 1.0 parts-per-billion (ppb) are simulated and the impacts are then assessed at device level. Under evaluation are the 10 most common elements encountered namely Al, Ca, Cr, Cu, Fe, Na, Ni, Zn, Co, Mg.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133334327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Measuring of phosphorous in silicon wafers by VPD-ICPMS 用VPD-ICPMS测定硅片中的磷
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-01 DOI: 10.1109/IPFA.2016.7564275
Hwee Hong Eng, Wei Teck Yeo, E. Er, S. Zhao
{"title":"Measuring of phosphorous in silicon wafers by VPD-ICPMS","authors":"Hwee Hong Eng, Wei Teck Yeo, E. Er, S. Zhao","doi":"10.1109/IPFA.2016.7564275","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564275","url":null,"abstract":"Phosphorus is typically a common dopant used in wafer manufacturing. Measuring of phosphorous in Si-wafer is always demanding and matrix interferences is always a problem in VPD ICPMS. It is reported here the measuring of phosphorus in VPD matrix using ICPMS.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":" 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120833241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Long-term reliability of lead-free electronic systems 无铅电子系统的长期可靠性
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-01 DOI: 10.1109/IPFA.2016.7564306
G. Pandian, Gopala Krishnan Ramaswami, M. Hodkiewicz, E. Cripps, M. Pecht
{"title":"Long-term reliability of lead-free electronic systems","authors":"G. Pandian, Gopala Krishnan Ramaswami, M. Hodkiewicz, E. Cripps, M. Pecht","doi":"10.1109/IPFA.2016.7564306","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564306","url":null,"abstract":"Industries that have been excluded from being required to transition to lead-free electronics (based on RoHs legislation) are nevertheless under economic pressure to transition. However, they are hesitant due to the unavailability of long-term reliability data. This study investigates degradation mechanisms of lead-free electronics systems that were used or stored for 10 years in laboratory conditions. A series of system diagnosis were conducted to evaluate the overall functional health of these computer systems. Accelerated life-time model from the literature was used to estimate the lifetime of the systems using their operating conditions input. These results were compared with current functionality status of the systems.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129724517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast and efficient method to detect probe mark and wire bond induced pad damage 一种快速有效的检测探针标记和焊丝损伤的方法
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-01 DOI: 10.1109/IPFA.2016.7564272
Jethro Tan, Gary H. G. Chan, W. F. Kho
{"title":"Fast and efficient method to detect probe mark and wire bond induced pad damage","authors":"Jethro Tan, Gary H. G. Chan, W. F. Kho","doi":"10.1109/IPFA.2016.7564272","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564272","url":null,"abstract":"Under non-optimized wafer probe and wire bonding conditions, pad cratering/interlevel dielectric (ILD) cracks may result in an electrical failure. The conventional procedures to analyse these failures include fault localization, optical inspection, SEM inspection and Focused Ion Beam cross-section, which can be very time consuming. In this paper, we introduce a method to detect these failure more expeditiously using optical microscopy and chemical delayering.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124491378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Resolution of missing silicide layer on P-type MOSFET caused by water droplet 水滴引起的p型MOSFET硅化物缺失层的解析
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-01 DOI: 10.1109/IPFA.2016.7564271
Siew Mei Teo, Khairul Aiman Yusof, N. Hat
{"title":"Resolution of missing silicide layer on P-type MOSFET caused by water droplet","authors":"Siew Mei Teo, Khairul Aiman Yusof, N. Hat","doi":"10.1109/IPFA.2016.7564271","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564271","url":null,"abstract":"Some of the wafer fabrication defects are unable to be screened out during final test. It is inevitable that these defective units will reach customer. This paper aims to discuss on the failure analysis approach and resolution of wafer fabrication defect, missing silicide layer.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125355354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluation of Fan-out Wafer Level Package strength by three-point bending testing 用三点弯曲测试评估扇形圆片级封装强度
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-01 DOI: 10.1109/IPFA.2016.7564304
C. Xu, Z. Zhong, W. Choi
{"title":"Evaluation of Fan-out Wafer Level Package strength by three-point bending testing","authors":"C. Xu, Z. Zhong, W. Choi","doi":"10.1109/IPFA.2016.7564304","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564304","url":null,"abstract":"The Fan-out Wafer Level Package (FOWLP) becomes more attractive because of its flexibility for integration of diverse devices in a very small form factor. As the FOWLP is composed of various materials, the proper structural and material designs are important to meet reliability requirements. In this study, mechanical properties of FOWLPs with different structures were evaluated by a three-point-bending test method. It aims to understand the effect of structural factors on package strength and its reliability.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115159116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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