2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)最新文献

{"title":"Proposal of local deep level transient spectroscopy using super-higher-order scanning nonlinear dielectric microscopy and 2-dimensional imaging of trap distribution in SiO2/SiC interface","authors":"N. Chinone, R. Kosugi, Yasunori Tanaka, S. Harada, H. Okumura, Yasuo Cho","doi":"10.1109/IPFA.2016.7564317","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564317","url":null,"abstract":"A new technique for microscopically evaluating insulator-semiconductor interface traps is proposed. The proposed technique is applied for SiO2/SiC stack structure and 2-dimensional imaging of interface traps is performed.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121379087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Challenges and improvement of reliability in advanced wafer level packaging technology","authors":"S. Yoon","doi":"10.1109/IPFA.2016.7564245","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564245","url":null,"abstract":"The number of WLCSP (Wafer Level Packages) used in semiconductor packaging has experienced significant growth since its introduction in 1998. The growth has been driven primarily by mobile consumer products because of the small form factor and high performance enabled in the package design. And it is also attractive to WE (wearable electronics) and IoT (Internet of Things) products. Although WLCSP is now a widely accepted package option, the initial acceptance of WLCSP was limited by concerns with the SMT assembly process and the fragile nature of the exposed silicon inherent in the package design. Assembly skills and methods have improved since the introduction of the package; however, damage to the silicon remains a concern. The side or top of the die continue to be exposed after dicing the wafer and the silicon continues to be at risk for chipping, cracking, and other handling damage during the assembly process. This paper introduces eWLB (embedded Wafer Level Ball Grid Array) /FO-WLP (fanout-WLP) and eWLCSP (encapsulated WLCSP) for its improved and advanced reliability [1], In these new packages EMC is applied to all exposed silicon surfaces on the die. The manufacturing process leverages existing high volume manufacturing methods with exceptionally high process yields. eWLB is a type of FO-WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. For eWLCSP, the applied coating protects the silicon and fragile dielectrics to prevent handling damage during dicing and assembly operations, effectively providing a packaged part in the form factor of a WLCSP. In manufacturing process, the product wafer is thinned and diced first. The dies are then reconstituted into a wafer form and standard methods are used to apply dielectrics, thin film metals, and solder bumps. The resulting structure is identical to conventional WLCSP products with the exception of the protective sidewall coating. This paper discusses the improvement of reliability, both component level and board level (drop and Temperature Cycle on Board). The key attributes of the new package as well as the manufacturing process used to create it are to be presented. Experimental reliability data and failure mode are studied and compared to conventional WLCSP products.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115326992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Detection of solder bump marginal contact resistance degradation using 4-point resistance measurement method","authors":"M. Seungje, D. Nagalingam, A. Quah, G. Ang, H. Ng, A. Teo, N. Xu, Z. Mai, J. Lam","doi":"10.1109/IPFA.2016.7564237","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564237","url":null,"abstract":"Wafer Level Chip Scale Packaging (WLCSP) involves more bumping process steps after receiving the passivated product wafer from the foundry manufacturing line. As wafer sort is usually tested after the bumping process, on the solder bump, any process drift during bumping, especially the contact resistance degradation at the Aluminum (Al) pad to Redistribution Layer (RDL) interface or RDL to solder bump interface, can also lead to severe yield loss. In such situations, foundries still play a critical role in working with the bump house to determine the cause of failure. This paper describes three case studies on how the four-point resistance measurement method was employed effectively on the failure pad to accurately detect a marginal increase in bump stack resistance resulting in yield loss and to further localize the root cause of high interface contact resistance.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122398248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IGBT collector-emitter failure mechanism","authors":"S. S. Lee, W. Tham, C. K. Ang","doi":"10.1109/IPFA.2016.7564276","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564276","url":null,"abstract":"Collector-Emitter breakdown voltage failure of IGBT can be caused by leakage characteristic or solely reverse blocking voltage issue. The involvement of potential defect could be located near the front side, where the main transistor construction located (the top side), chip temination edge and down to the backside where the fieldstop layer takes place. This paper basically outlined the failure mechanisms based on the Current-Voltage characteristic and they were then visualized through the physical analyses, and they were proven from the failure analyses findings.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122562922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Recent advances of RTN technique towards the understanding of the gate dielectric reliability in trigate FinFETs","authors":"S. Chung","doi":"10.1109/IPFA.2016.7564242","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564242","url":null,"abstract":"The experimental RTN-trap profiling method bas been demonstrated on both planar and trigate MOSFETs. It was achieved by a simple experimental method to take the 2D profiling of the RTN-trap in both oxide depth (vertical) and channel (lateral) directions in the gate oxide. Then, by arranging various 2D fields for the device stress condition, the positions of RTN traps can be precisely controlled. The positions of RTN-traps can be manipulated, showing significant advances for the understanding of the trap generation and the impact on the device reliability. Results have demonstrated why trigate exhibits much worse reliability than the planar ones.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"309 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122698563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Developments in SPM technologies for semiconductor failure analysis","authors":"Wanxin Sun","doi":"10.1109/IPFA.2016.7564316","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564316","url":null,"abstract":"With the increase in circuitry complexity and shrinkage in device dimensions, failure analysis (FA) plays a more important role in identifying root cause and thus in yield enhancement. Scanning probe microscopy (SPM) has been extensively used in semiconductor FA labs. With the shrinkage in device dimensions, higher challenges are casted on AFM technology. In this article, we will discuss the challenges and report our recent progress in tackling them, including improving spatial resolution and detection sensitivity.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122158516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mitigation of thin wafer handling issues in TSV (Through Silicon Via) fabrication for advanced packaging applications","authors":"V. N. Sekhar, R. Qin, S. Wickramanayaka","doi":"10.1109/IPFA.2016.7564305","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564305","url":null,"abstract":"Present study focuses on various thin wafer handling issues associated with via-last TSV fabrication integration schemes. Thin wafer handling methodology play very key role in any successful TSV interposer fabrication. Zonebond TBDB method is selected for this evaluation and critically analysed issues encountered in various fabrication steps like PECVD, PVD, etching, curing and CMP processes. Thin TSV wafer fabrication is always challenging as thin wafers are instable and more prone to failures in various fabrication environments. Hence it is timely to establish robust thin wafer handling schemes that promote seamless TSV interposer wafer fabrication. Extensive TBDB and process integration DOE has been conducted to mitigate these issues.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129955646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"BGA packaged IC sample preparing for electrical failure analysis","authors":"Quande Zhang, Y. Che, Jinglong Li, Binghai Liu","doi":"10.1109/IPFA.2016.7564260","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564260","url":null,"abstract":"As far as CMOS technology in nanometer-scale and metal layers increasing, failure analysis (FA) on packaged semiconductor device is typically from backside. This paper is to introduce some alternative backside sample preparation methods on ball grid array (BGA) packaged device, according to the circuit board configuration, failure types, analysis types as well as equipment requirement.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127776566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A thermo mechanical finite element modeling approach to solving stress induced passivation failures","authors":"F. Mirza, E. J. Khor, Fook Hong Lee, C. Premachandran, W. Yi, Juan Boon Tan, C. Graas, P. Justison","doi":"10.1109/IPFA.2016.7564315","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564315","url":null,"abstract":"Multi-layered systems are susceptible to cracking and or delamination upon temperature cycling. Passivation integrity test (PIT) is widely leveraged to assess and qualify the mechanical integrity of the passivation films (oxide, nitride) deposited on metal conductor. Cracking/delamination in the passivation film over the metal line results in moisture diffusion and may lead to metal corrosion. Therefore, it is imperative to identify the key geometric and process parameters that significantly affect the passivation integrity and understand the physics-of-failure in order to have a reliable structure. This paper demonstrates the failure assessment and mitigation in passivation films for a leading technology node chip during PIT. A finite element (FE) stress-strain model of the test vehicle (TV) is built to provide fundamental understanding of the effect of the critical input design parameters including the Aluminum (Al) line layout, Al space, Al width, and the passivation thickness on the passivation stress level. The FE model is validated with the experimental pass/fail data and is further leveraged to mitigate the passivation cracking issue. The effect of Al plastic behavior on the interfacing passivation layer is highlighted to accurately predict and understand the failure mechanism.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121736801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comprehensive physical and chemical characterization of the galvanic corrosion induced failures","authors":"Yixin Chen, Younan Hua, B. S. Khoo, Henry Leong, Vanie Bagulbagul, Yansong Wang, Yanlin Pan, E. Chan, Maohua Chen, Jing Yuan Wang, Yue Shen, Zilu Niu, J. Goh, E. Abella, Xiaomin Li","doi":"10.1109/IPFA.2016.7564312","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564312","url":null,"abstract":"The galvanic corrosion induced failures have been investigated for three cases in PCB, TFT touch screen and wire bonding industries using comprehensive physical and chemical characterization methods. Obvious evidences of anode oxidation and corrosive ions were found for all three cases. Characterization methodology should be tailored based on different situations.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115957352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}