{"title":"High resolution 3D X-ray microscopy for streamlined failure analysis workflow","authors":"C. Y. Liu, P. S. Kuo, C. Chu, A. Gu, J. Yoon","doi":"10.1109/IPFA.2016.7564285","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564285","url":null,"abstract":"High resolution 3D X-ray microscopy is a powerful non-destructive technology to inspect internal failure of IC packages. Here we present a correlative workflow by combining thermal emission microscopy, high resolution 3D X-ray microscopy and dual-beam focused ion beam microscopy to analyze a failed FCBGA package.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134442996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. A. F. Othman, S. F. Wan Muhammad Hatta, N. Soin
{"title":"Performance of 7nm stress-engineered nFinFETs based on stressors consideration for different channel material","authors":"N. A. F. Othman, S. F. Wan Muhammad Hatta, N. Soin","doi":"10.1109/IPFA.2016.7564297","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564297","url":null,"abstract":"Selecting the material used as the device channel which connects the source to drain region is vital as it will affect the conductivity of the transistor. Recently, germanium was actively used as the diffusion material for source/drain and channel properties mainly for ρ type FinFET, however rarely in η type FinFET. This paper investigates the device performance of 7nm nFinFET for their various types of stressor: channel and source/drain stressor by employing germanium as diffusion materials which indicates the strain applied to the device investigated. It was observed that with the incorporation of germanium inside silicon channel (depending on the ratio of Si1-xGex) and reducing the diffused germanium inside source/drain region, the Id-Vg characteristics seems to be better and shows enhanced performance. It was also observed that the drain current for nFinFET in linear mode can be increased up to 60% with the incorporation of germanium and by increasing the mole fraction of germanium inside source/drain region, the drain current can reduce up to 40% and 30% for silicon and silicon germanium channel respectively. In addition, with only 15%-30% of germanium present inside the source/drain region, the device seems to have a better performance with higher drain current.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131635674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Addressing the sample preparation challenges in failure analysis of wafer level chip scale package mounted inside a customer camera module","authors":"Jason H. Lagar, Rudolf A. Sia","doi":"10.1109/IPFA.2016.7564264","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564264","url":null,"abstract":"One significant application of Wafer Level Chip Scale Package (WLCSP) is in opto-electronics and CCD image processing. This includes cellphone camera module, notebook or computer camera module, video telephone and many more. Its package size represents a real advantage for designers of camera modules and is the ideal choice for highly space-constrained camera applications. One complex part though, is when the WLCSP unit failed during customer electrical testing or in the field. Failure analysis of the failing WLCSP unit mounted inside a camera module will be very challenging. The camera module needs to be opened to gain access on the WLCSP part, demount it and proceed to reballing process to enable further electrical verification and fault isolation analysis. This paper discusses the evaluations done in demounting the WLCSP unit mounted inside a customer camera module. Combinations of thermo-mechanical process and parallel lapping were used to demount the WLCSP unit. The established process enabled the electrical verification, fault isolation and further destructive analysis of WLCSP customer return mounted inside a camera module.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131768192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reliability and risk assessment from accelerated test result and field modeling: Delamination issue case study for automotive analog parts and sensors","authors":"C. Bergès, A. Feybesse, W. A. R. Othman","doi":"10.1109/IPFA.2016.7564314","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564314","url":null,"abstract":"For risk assessments in automotive semiconductor industry, while a typical field modeling uses failure mileages, a new time-based approach was implemented for a delamination issue on analog and sensor products. It highlighted a bimodality coherent with the failure analysis conclusions and with the two phases in the product life. Modeling per impacted wafer allowed to reveal specific profiles for some wafers. Modeling on Reliability Temperature Humidity Bias (THB) test results was also performed and compared to the field modeling.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117004485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. G. Yoon, J. Hyung, U. H. Jeong, S. Chan, J. Jang
{"title":"Wear-out failure modes and mechanism analysis of self-ballasted LED lamps via after-sale service data","authors":"Y. G. Yoon, J. Hyung, U. H. Jeong, S. Chan, J. Jang","doi":"10.1109/IPFA.2016.7564277","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564277","url":null,"abstract":"High reliability and long life of self-ballasted LED lamps are a very important lighting source used our in daily life. So we have studied the Wear-out failure modes and reproduced it in a short time by using an accelerated operational life test.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129608838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Andrew C. Sabate, Norazfar Nordin, Benedict Jimenez
{"title":"Fuse trim links physical analysis methodology","authors":"Andrew C. Sabate, Norazfar Nordin, Benedict Jimenez","doi":"10.1109/IPFA.2016.7564256","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564256","url":null,"abstract":"Fuse trim links failure on analog devices can cause wrong Vref value, incorrect I2C address, incorrect frequency setting, etc. The fuse trim links failure can either be unblown or mistakenly blown during the trimming process. To validate, if blown or unblown, physical analysis is needed to check the trim links. This paper aims to discuss the different physical analysis methodology to check the integrity of trim links.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128916405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Gambino, Y. Watanabe, Y. Kanuma, B. Greenwood, D. Price, A. Suwhanov, S. Hose, O. Whear
{"title":"Imaging of strain from deep trenches using X-Ray Diffraction Imaging (XRDI)","authors":"J. Gambino, Y. Watanabe, Y. Kanuma, B. Greenwood, D. Price, A. Suwhanov, S. Hose, O. Whear","doi":"10.1109/IPFA.2016.7564309","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564309","url":null,"abstract":"X-Ray Diffraction Imaging (XRDI) is used to non-destructively image strain in Si associated with deep trench isolation in high voltage devices. The XRD images show that there is dark contrast associated with deep trenches which is indicative of strain and defects in a material. Using defect etching, it is shown that there is a tendency for higher dislocation densities in regions where there is dark contrast in the XRD image. These results suggest that XRD imaging can be a useful tool for optimizing layout and processes for devices with deep trench isolation.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130924558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Logic circuit analysis and TEM inspection of IDDQ logic leakage","authors":"Ang Chung Keow, Yong Foo Khong","doi":"10.1109/IPFA.2016.7564279","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564279","url":null,"abstract":"The decreasing of technology node has made process of failure analysis become difficult. This paper outlines electrical fault localization method on IDDQ logic leakage failure. Upon fault localization, a complete analysis through TEM was performed for identification and further understanding of the failure mechanism eventually led to root cause finding.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121075672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rowin V. Galarce, Francis Nikolai Lupena, Benedict Jimenez, Siew Mei Teo
{"title":"Failure analysis defect localization of a metal stringer defect on a monolithic step-up DC-DC converter","authors":"Rowin V. Galarce, Francis Nikolai Lupena, Benedict Jimenez, Siew Mei Teo","doi":"10.1109/IPFA.2016.7564269","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564269","url":null,"abstract":"There is a recent influx of failures on an automotive device particularly on a Monolithic Step-Up DC-DC Converter. Difficulty arises on the defect localization of the metal stringer since majority of the failing units have different electrical signatures wherein some returned units are failing at field, 0Km failure or failing at higher temperature which was either verified electrically failing at ATE (Automated Testing Equipment), curve trace verification or bench test simulation. This paper aims to show the different FA techniques particularly bench test verification, OBIRCH, Emission Microscopy, Micro probing, FIB and EDX which was utilized to pinpoint the exact failure mechanism. Also, on the wafer fabrication site, a root cause was put in place to minimize if not eliminate these kinds of failure.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122437073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Physical characterization and sample preparation for MEMS devices","authors":"S. Lee, P. Ang, Z. Mo, S. P. Zhao","doi":"10.1109/IPFA.2016.7564263","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564263","url":null,"abstract":"Device characterization and failure analysis of micro-electro-mechanical systems (MEMS) devices are vital steps to improve the device performance and understand the root cause of low yield. Challenges are often encountered when applying most traditional failure analysis or sample preparation methods on MEMS devices. Due to the cavities and the “floating” structures in these devices, the “floating” structures can be damaged or distorted without a good protection prior to cutting or grinding. This paper demonstrates the development of a suitable protective coating layer before FIB milling to prevent the formation of an artifact/re-deposition layer at the bottom of the MEMS device handle.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131753879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}