2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)最新文献

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Abrasive wear mechanism of Nickel plating in contact to Polyethylene Terephthalate Plastic(PET) 镀镍与聚对苯二甲酸乙二醇酯塑料(PET)接触的磨粒磨损机理
C. Meng, S. Dubey, Y. Srivastava
{"title":"Abrasive wear mechanism of Nickel plating in contact to Polyethylene Terephthalate Plastic(PET)","authors":"C. Meng, S. Dubey, Y. Srivastava","doi":"10.1109/IPFA.2016.7564301","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564301","url":null,"abstract":"This paper discusses the abrasive mechanism of Nickel plating surfaces when in contact with Polyethylene Terephthalate Plastic (PET). Abrasive wear is the loss of materials due to interactive movement of hard particles over the metal surface. Abrasive wear on surfaces is common in metal-to-non-metal or metal-to-metal interaction depending on the difference in hardness of such materials. Here, the abrasive mark mechanism due to plastic-to-Metal (Nickel) interaction has been explained in detail through a series of simulated experiments and analysis. It has been established that the roughness of Nickel and the particle transfer from Ni to PET play key roles in the generation of abrasive marks.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132817076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast backside fault isolation for parametric issue in Ball Grid Array (BGA) packages by selective area thinning 基于选择性区域细化的球栅阵列(BGA)封装参数故障快速隔离
Foo Loke Sheng, Lee Weng Hong, W. A. R. Othman
{"title":"Fast backside fault isolation for parametric issue in Ball Grid Array (BGA) packages by selective area thinning","authors":"Foo Loke Sheng, Lee Weng Hong, W. A. R. Othman","doi":"10.1109/IPFA.2016.7564326","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564326","url":null,"abstract":"As silicon technology scales down in size, front side fault localization for parametric failures in semiconductor devices has become more difficult. This is due to the increasing number of metallization layers. Hence, backside fault isolation techniques are employed. Challenges arise when the device packages are not designed for backside analysis. This is especially true for BGA (Ball Grid Array) packages. There are several approaches to perform backside analysis on BGA packages but some of them may be time and resources consuming. One such example is repackaging. This paper proposes a method to selectively thin the BGA package but yet preserves the electrical integrity and package spheres of interest for quick backside electrical analysis.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134184426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Effect of grade doping buffer layer on SEE failure in VDMOSFET 级掺杂缓冲层对VDMOSFET SEE失效的影响
Yunpeng Jia, Ling Peng, Hongyuan Su, D. Hu, Yuehua Wu
{"title":"Effect of grade doping buffer layer on SEE failure in VDMOSFET","authors":"Yunpeng Jia, Ling Peng, Hongyuan Su, D. Hu, Yuehua Wu","doi":"10.1109/IPFA.2016.7564299","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564299","url":null,"abstract":"Single event burnout (SEB) is a common single event effect (SEE) occur in VDMOSFET, previous studies have indicated the strong relationship between the device's secondary breakdown voltage and the SEB threshold voltage. This paper presents a grade doping buffer layer structure to improve the device's secondary breakdown voltage so that enhance the resistance to SEE. Through detailed simulation, it has been verified that optimized grade doping buffer layer can decrease the peak value of the electric field, significantly improve the parasitic bipolar turn-on current and the SEB threshold voltage. Moreover, compared to non-buffer layer and constant doping buffer layer structure, the optimized grade doping buffer structure is a more effective structure in SEE hardened VDMOSFET.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132898119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Defect detection method using statistical image processing of scanning acoustic tomography 基于统计图像处理的扫描声层析成像缺陷检测方法
K. Sakai, O. Kikuchi, K. Kitami, M. Umeda, Shigeru Ohno
{"title":"Defect detection method using statistical image processing of scanning acoustic tomography","authors":"K. Sakai, O. Kikuchi, K. Kitami, M. Umeda, Shigeru Ohno","doi":"10.1109/IPFA.2016.7564303","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564303","url":null,"abstract":"This paper describes an inspection technique for detecting bonding defects in interfaces of stacked wafers that have complicated patterns. This technique detects the minute defects as statistical outliers from scanning acoustic tomography images that include the pattern formed repeatedly. The experimental results show that one-pixel size defects near the complicated patterns can be detected from ultrasound images.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122246376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Simulation assisted uncovering and understanding of complex failures in 28nm microprocessor devices 模拟有助于揭示和理解28nm微处理器器件中的复杂故障
Dnyan Khatri, V. Narang, M. Ho, Komal Pandey, Ran Yu
{"title":"Simulation assisted uncovering and understanding of complex failures in 28nm microprocessor devices","authors":"Dnyan Khatri, V. Narang, M. Ho, Komal Pandey, Ran Yu","doi":"10.1109/IPFA.2016.7564249","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564249","url":null,"abstract":"With rapid developments in semiconductor manufacturing technologies, new and more complicated challenges emerge in the Failure Analysis space. The real challenge arises when similar electrical data is obtained from transistor nano-probing from completely different defect types. Accurate data interpretation is therefore the key to unraveling and understanding the root causes of failure. This paper emphasizes on the use of simulation as a tool to identify key differences in electrical data to successfully zero in on the root causes of failure, thus enabling wafer fabs to take appropriate corrective measures in mitigating such failures. Successful case studies involving these techniques will also be discussed.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115994187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The application of pulse IV function in nano-prober system 脉冲IV函数在纳米探针系统中的应用
Yu Te Lee, Jeng Hung Pan, Zenniss Huang, S. Liu, Y. P. Chang, J. Lin
{"title":"The application of pulse IV function in nano-prober system","authors":"Yu Te Lee, Jeng Hung Pan, Zenniss Huang, S. Liu, Y. P. Chang, J. Lin","doi":"10.1109/IPFA.2016.7564289","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564289","url":null,"abstract":"A Nano-Prober System, combining scanning electron microscope (SEM), prober system, and measurement instrument is widely used in failure analysis field for soft localization. Most applications of the nano-prober system utilizes Direct Current (DC) electrical test to measure device characteristics. However, some failure mechanisms can hardly be diagnosed by applying traditional DC measurement. In this paper, Alternating Current (AC) pulse IV functional measurement was applied in soft failure study. A case screened out from speed test is adopted in this study. After non-abnormal is diagnosed via DC measurement, pulse IV measurement is used to conduct further measurement. While using pulse IV measurement method, the rising time of defective die is significantly longer than normal die, which is a convincing evidence that die failure is strongly related timing issue. Further Physical Failure Analysis (PFA) demonstrates that the poor connection between Poly and Contact layer is the major cause of the failure. The result of this paper indicates the effectiveness of pulse IV measurement in failure analysis.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123724804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
FBGA 55nm SOC PLL failure analysis through OBIRCH FBGA 55nm SOC锁相环失效分析
L. K. Heng, Liew Chiun Ning
{"title":"FBGA 55nm SOC PLL failure analysis through OBIRCH","authors":"L. K. Heng, Liew Chiun Ning","doi":"10.1109/IPFA.2016.7564270","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564270","url":null,"abstract":"Ongoing miniaturization in process node technology used in fabricating integrated circuits (ICs) has enhanced chip performance but at the same time this has induced subtle defects. As a result, Failure Analysis (FA) has become increasingly important for root cause analysis to enable wafer fab process improvement and enable design fix. This paper presents a novel FA approach on real case Phase Locked Loop (PLL) functional failure induced in Electrostatic Discharge (ESD) Machine Model (MM) zap by incorporating Optical Beam Induced Resistance Change (OBIRCH), extensive layout study, Conductive Atomic Force Microscopy (CAFM), and Passive Voltage Contrast (PVC) for defect localization.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125275099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dynamic NBTI simulation coupling with self-heating effect in SOI MOSFETs SOI mosfet中耦合自热效应的动态NBTI仿真
Xiangbin Li, Chenyue Ma, Lining Zhang, F. Sun, Xinnan Lin, M. Chan
{"title":"Dynamic NBTI simulation coupling with self-heating effect in SOI MOSFETs","authors":"Xiangbin Li, Chenyue Ma, Lining Zhang, F. Sun, Xinnan Lin, M. Chan","doi":"10.1109/IPFA.2016.7564244","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564244","url":null,"abstract":"A methodology for simulating the device performance degradation considering the coupling effect of NBTI and SHE in SOI p-MOSFETs is proposed. NBTI models and thermal network are implanted into HiSIM with instantaneous parameter update during the transient simulation. The simulation results show that decoupling simulation will lead to non-ignorable inaccuracy.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114622207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Understanding testing for dynamic fault isolation of microprocessors 了解微处理器动态故障隔离测试
V. Ravikumar
{"title":"Understanding testing for dynamic fault isolation of microprocessors","authors":"V. Ravikumar","doi":"10.1109/IPFA.2016.7564238","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564238","url":null,"abstract":"Dynamic Fault Isolation is a very important step in the Failure Analysis process flow of VLSI circuits over the last decade. Key factors in successful dynamic FI include understanding the test methodology, knowledge of the design for test (DFT) features such as BIST and SCAN, and in interpretation of the fault isolation signals. The invited talk will also discuss a few recent advances that help with the challenges of dynamic fault isolation.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130099811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Sleep mode IDDQ failure analysis in 28nm mobile application 28nm移动应用中睡眠模式IDDQ失效分析
G. Qian, Parker Miao, SoonFatt Ng
{"title":"Sleep mode IDDQ failure analysis in 28nm mobile application","authors":"G. Qian, Parker Miao, SoonFatt Ng","doi":"10.1109/IPFA.2016.7564240","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564240","url":null,"abstract":"Through the investigation of sleep mode IDDQ failure encounter in fabrication of a 28nm mobile application IC, this paper will demonstrate the Failure analysis techniques applicable for leakage source detection involving activation of power management feature rather than pure DC bias, we will also discuss the potential process/design weak point and proposed solution in deep submicron technology node.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124592865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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