FBGA 55nm SOC PLL failure analysis through OBIRCH

Abstract

Ongoing miniaturization in process node technology used in fabricating integrated circuits (ICs) has enhanced chip performance but at the same time this has induced subtle defects. As a result, Failure Analysis (FA) has become increasingly important for root cause analysis to enable wafer fab process improvement and enable design fix. This paper presents a novel FA approach on real case Phase Locked Loop (PLL) functional failure induced in Electrostatic Discharge (ESD) Machine Model (MM) zap by incorporating Optical Beam Induced Resistance Change (OBIRCH), extensive layout study, Conductive Atomic Force Microscopy (CAFM), and Passive Voltage Contrast (PVC) for defect localization.