Fast backside fault isolation for parametric issue in Ball Grid Array (BGA) packages by selective area thinning

Abstract

As silicon technology scales down in size, front side fault localization for parametric failures in semiconductor devices has become more difficult. This is due to the increasing number of metallization layers. Hence, backside fault isolation techniques are employed. Challenges arise when the device packages are not designed for backside analysis. This is especially true for BGA (Ball Grid Array) packages. There are several approaches to perform backside analysis on BGA packages but some of them may be time and resources consuming. One such example is repackaging. This paper proposes a method to selectively thin the BGA package but yet preserves the electrical integrity and package spheres of interest for quick backside electrical analysis.