用于电气故障分析的BGA封装IC样品制备

2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI:10.1109/IPFA.2016.7564260

Quande Zhang, Y. Che, Jinglong Li, Binghai Liu

{"title":"用于电气故障分析的BGA封装IC样品制备","authors":"Quande Zhang, Y. Che, Jinglong Li, Binghai Liu","doi":"10.1109/IPFA.2016.7564260","DOIUrl":null,"url":null,"abstract":"As far as CMOS technology in nanometer-scale and metal layers increasing, failure analysis (FA) on packaged semiconductor device is typically from backside. This paper is to introduce some alternative backside sample preparation methods on ball grid array (BGA) packaged device, according to the circuit board configuration, failure types, analysis types as well as equipment requirement.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"BGA packaged IC sample preparing for electrical failure analysis\",\"authors\":\"Quande Zhang, Y. Che, Jinglong Li, Binghai Liu\",\"doi\":\"10.1109/IPFA.2016.7564260\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As far as CMOS technology in nanometer-scale and metal layers increasing, failure analysis (FA) on packaged semiconductor device is typically from backside. This paper is to introduce some alternative backside sample preparation methods on ball grid array (BGA) packaged device, according to the circuit board configuration, failure types, analysis types as well as equipment requirement.\",\"PeriodicalId\":206237,\"journal\":{\"name\":\"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-07-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.2016.7564260\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2016.7564260","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

随着纳米级CMOS技术和金属层数的不断增加，对封装半导体器件的失效分析通常是从背面进行的。本文根据电路板配置、故障类型、分析类型以及设备要求，介绍了BGA封装器件背面样品制备的几种备选方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

BGA packaged IC sample preparing for electrical failure analysis

As far as CMOS technology in nanometer-scale and metal layers increasing, failure analysis (FA) on packaged semiconductor device is typically from backside. This paper is to introduce some alternative backside sample preparation methods on ball grid array (BGA) packaged device, according to the circuit board configuration, failure types, analysis types as well as equipment requirement.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

自引率

0.00%

发文量