M. Seungje, D. Nagalingam, A. Quah, G. Ang, H. Ng, A. Teo, N. Xu, Z. Mai, J. Lam
{"title":"用四点电阻测量法检测凸点边缘接触电阻退化","authors":"M. Seungje, D. Nagalingam, A. Quah, G. Ang, H. Ng, A. Teo, N. Xu, Z. Mai, J. Lam","doi":"10.1109/IPFA.2016.7564237","DOIUrl":null,"url":null,"abstract":"Wafer Level Chip Scale Packaging (WLCSP) involves more bumping process steps after receiving the passivated product wafer from the foundry manufacturing line. As wafer sort is usually tested after the bumping process, on the solder bump, any process drift during bumping, especially the contact resistance degradation at the Aluminum (Al) pad to Redistribution Layer (RDL) interface or RDL to solder bump interface, can also lead to severe yield loss. In such situations, foundries still play a critical role in working with the bump house to determine the cause of failure. This paper describes three case studies on how the four-point resistance measurement method was employed effectively on the failure pad to accurately detect a marginal increase in bump stack resistance resulting in yield loss and to further localize the root cause of high interface contact resistance.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Detection of solder bump marginal contact resistance degradation using 4-point resistance measurement method\",\"authors\":\"M. Seungje, D. Nagalingam, A. Quah, G. Ang, H. Ng, A. Teo, N. Xu, Z. Mai, J. Lam\",\"doi\":\"10.1109/IPFA.2016.7564237\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Wafer Level Chip Scale Packaging (WLCSP) involves more bumping process steps after receiving the passivated product wafer from the foundry manufacturing line. As wafer sort is usually tested after the bumping process, on the solder bump, any process drift during bumping, especially the contact resistance degradation at the Aluminum (Al) pad to Redistribution Layer (RDL) interface or RDL to solder bump interface, can also lead to severe yield loss. In such situations, foundries still play a critical role in working with the bump house to determine the cause of failure. This paper describes three case studies on how the four-point resistance measurement method was employed effectively on the failure pad to accurately detect a marginal increase in bump stack resistance resulting in yield loss and to further localize the root cause of high interface contact resistance.\",\"PeriodicalId\":206237,\"journal\":{\"name\":\"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)\",\"volume\":\"68 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-07-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.2016.7564237\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2016.7564237","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Detection of solder bump marginal contact resistance degradation using 4-point resistance measurement method
Wafer Level Chip Scale Packaging (WLCSP) involves more bumping process steps after receiving the passivated product wafer from the foundry manufacturing line. As wafer sort is usually tested after the bumping process, on the solder bump, any process drift during bumping, especially the contact resistance degradation at the Aluminum (Al) pad to Redistribution Layer (RDL) interface or RDL to solder bump interface, can also lead to severe yield loss. In such situations, foundries still play a critical role in working with the bump house to determine the cause of failure. This paper describes three case studies on how the four-point resistance measurement method was employed effectively on the failure pad to accurately detect a marginal increase in bump stack resistance resulting in yield loss and to further localize the root cause of high interface contact resistance.