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2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)最新文献

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Advanced fault isolation techniques for 3D packaging 先进的三维封装故障隔离技术
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564284
Y. Chen, P. Lai, Q. Shi
{"title":"Advanced fault isolation techniques for 3D packaging","authors":"Y. Chen, P. Lai, Q. Shi","doi":"10.1109/IPFA.2016.7564284","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564284","url":null,"abstract":"3D packaging has become a popular technology along with the tendency of functionality and portability for electronic devices. Conventional fault isolation techniques face a great challenge for 3D packaging devices. 3D X-Ray laminography technique can capture three-dimensional information about the internal structure of an object. Magnetic current imaging technique is a non-destructive failure isolation technique at package levels. This paper introduces these two kinds of useful fault isolation techniques for 3D packaging. And case studies demonstrated the effectiveness of the advanced fault isolation techniques for 3D packaging.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124830895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Effect of formation temperature on quality of gate dielectric on germanium substrate 形成温度对锗衬底栅介质质量的影响
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564294
E. Wei, B. Tsui, Pin-Jiun Wu
{"title":"Effect of formation temperature on quality of gate dielectric on germanium substrate","authors":"E. Wei, B. Tsui, Pin-Jiun Wu","doi":"10.1109/IPFA.2016.7564294","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564294","url":null,"abstract":"Germanium metal-insulator-semiconductor (MIS) structure with HfO2/Al2O3/GeO2 gate stack have been demonstrated to exhibit good performance. In this work, the effect of formation temperature of the gate stack on the quality of the gate dielectric is investigated. It is found that the higher plasma oxidation temperature helps the GeO2 formation and less interface states. But the higher deposition temperature of the ALD high-k films may degrade the interface and result in higher leakage current.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117002532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrostatic Discharge (ESD) and Electrical Overstress (EOS) — The state of the art for methods of failure analysis, and testing in components and systems 静电放电(ESD)和电气超应力(EOS) -组件和系统中失效分析和测试方法的最新状态
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564251
S. Voldman
{"title":"Electrostatic Discharge (ESD) and Electrical Overstress (EOS) — The state of the art for methods of failure analysis, and testing in components and systems","authors":"S. Voldman","doi":"10.1109/IPFA.2016.7564251","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564251","url":null,"abstract":"Electrostatic Discharge (ESD) and Electrical Overstress (EOS) continue to impact semiconductor components and systems as technologies scale from micro-to nano-electronics. This paper focuses on the state of the art of electrostatic discharge (ESD) and electrical overstress (EOS), with an emphasis on failure mechanisms and testing. The tutorial provides a clear picture of EOS phenomena, ESD and EOS failure mechanisms, testing and testing standards, and new failure analysis techniques.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117186671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The statistics of set time of oxide-based resistive switching memory 氧化物基电阻性开关存储器的设定时间统计
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564324
Meiyun Zhang, S. Long, Guoming Wang, Zhaoan Yu, Yang Li, D. Xu, H. Lv, Qi Liu, E. Miranda, J. Suñé, Ming Liu
{"title":"The statistics of set time of oxide-based resistive switching memory","authors":"Meiyun Zhang, S. Long, Guoming Wang, Zhaoan Yu, Yang Li, D. Xu, H. Lv, Qi Liu, E. Miranda, J. Suñé, Ming Liu","doi":"10.1109/IPFA.2016.7564324","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564324","url":null,"abstract":"In this paper, the characteristics of the set time (t<sub>set</sub>) correlated with the initial off-state resistance (R<sub>off</sub>) were studied using a statistical method based on a Ti/ZrO<sub>2</sub>/Pt RRAM device. The data were collected by the width-adjusting pulse operation (WAPO) method. The Weibull distribution is used to analyze t<sub>set</sub> variation. Both the Weibull slope (β<sub>t</sub>) and scale factor (t<sub>set6</sub>3%) of t<sub>Set</sub> distributions increase logarithmically with R<sub>off</sub>. An analytical cell-based model was developed to explain the experimental statistics. Our result provides an inspiration on the switching uniformity and optimization of the tradeoff between the set speed-disturb dilemma.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133683625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Combinational logic analysis case studies using laser voltage probing 激光电压探测组合逻辑分析案例研究
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564246
Winson Lua, G. Ranganathan, V. Ravikumar, Angeline Phoa
{"title":"Combinational logic analysis case studies using laser voltage probing","authors":"Winson Lua, G. Ranganathan, V. Ravikumar, Angeline Phoa","doi":"10.1109/IPFA.2016.7564246","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564246","url":null,"abstract":"Combinational logic analysis has been introduced to improve fault isolation when using laser voltage probing on standard cells. The technique has been shown to offer more reliable isolation within a shorter time thereby increasing FI efficiency. This paper uses interesting case studies to showcase how incorporating into conventional laser voltage probing significantly improves the success rate of failure analysis.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131662254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Improvement of top-down delayering techniques on advanced technology nodes 先进技术节点自顶向下分层技术改进
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564253
T. Hrncír, H. H. Yap, E. Moyal, J. Teshima
{"title":"Improvement of top-down delayering techniques on advanced technology nodes","authors":"T. Hrncír, H. H. Yap, E. Moyal, J. Teshima","doi":"10.1109/IPFA.2016.7564253","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564253","url":null,"abstract":"An improved method of a planar IC sample delayering by FIB is proposed. The sample cleaving and FIB milling from two directions increases the quality of the delayered area. SEM allows accurate endpointing of the delayering on the layer of interest. The method allows to increase the delayered sample area significantly.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132155831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Surface elemental quantification of Au-Pd pre-plated leadframe by means of X-ray Photoelectron Spectroscopy 用x射线光电子能谱法定量Au-Pd预镀引线框架的表面元素
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564265
Y. Kee, S. R. Esa, B. A. Rahim, W. A. W. Ismail
{"title":"Surface elemental quantification of Au-Pd pre-plated leadframe by means of X-ray Photoelectron Spectroscopy","authors":"Y. Kee, S. R. Esa, B. A. Rahim, W. A. W. Ismail","doi":"10.1109/IPFA.2016.7564265","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564265","url":null,"abstract":"Quantification of sample with Palladium (Pd) and Gold (Au) using X-ray Photoelectron Spectroscopy (XPS) could be a great challenge due to the overlapping of Pd, Au and Oxygen photoelectron lines. Conventional baseline subtraction method is not applicable when the content of Pd is too low. A metrology for Pd-Au pre-plated leadframe surface atomic percent quantification using XPS deconvolution method was demonstrated to be able to quantify Pd-Au pre-plated leadframe with low Pd content. Three XPS wide scans were performed on the same analysis spot at energy resolutions of 1 eV/step, 0.5 eV/step and 0.1 eV/step respectively. The same metrology was utilized for atomic percent quantification and compare the accuracy based on deconvolution results.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124919236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automatic processing scheme for low laser invasiveness electro optical frequency mapping mode 低激光侵入性电光频率测绘模式的自动处理方案
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564255
A. Boscaro, S. Jacquir, K. Sanchez, H. Terada, P. Perdu, S. Binczak
{"title":"Automatic processing scheme for low laser invasiveness electro optical frequency mapping mode","authors":"A. Boscaro, S. Jacquir, K. Sanchez, H. Terada, P. Perdu, S. Binczak","doi":"10.1109/IPFA.2016.7564255","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564255","url":null,"abstract":"Electro optical techniques are efficient backside contactless techniques usually used for design debug and defect location in modern VLSI. Unfortunately, the signal to noise ratio is quite low and depends on laser power with potential device stress due to long acquisition time or high laser power, especially in up to date technologies. Under these conditions, to maintain a good signal or image quality, specific signal or image processing techniques can be implemented. In this paper, we proposed a new spatial filtering by stationary wavelets and contrast enhancement which allows the use of low laser power and short acquisition time in image mode.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132757172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Failure analysis on MEMS resonator device in wafer fabrication MEMS谐振器在晶圆制造中的失效分析
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564329
H. Ng, N. Xu, A. Teo, G. Ang, A. Quah, Dayanand, C. Q. Chen, Z. Mai, J. Lam
{"title":"Failure analysis on MEMS resonator device in wafer fabrication","authors":"H. Ng, N. Xu, A. Teo, G. Ang, A. Quah, Dayanand, C. Q. Chen, Z. Mai, J. Lam","doi":"10.1109/IPFA.2016.7564329","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564329","url":null,"abstract":"This paper demonstrates a new de-process flow for MEMS resonator DRG (dc Resistance to Ground) failure analysis, using electrical fault isolation tool of TTVA to locate the defect site. After all, cutting method was performed to de-process MEMS from Si Cap, followed by SEM inspection to successfully observe the physical defect point. Auger analysis was then carried out on the defect point to identify the element contains, hence the root cause of preventing of Carbon and Mo was confirmed.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130239411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Failure investigation of a die crack on a CMOS low dropout regulator device CMOS低差稳压器件的模具裂纹失效研究
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564273
Francis Nikolai Lupena, Siew Mei Teo, Rowin V. Galarce
{"title":"Failure investigation of a die crack on a CMOS low dropout regulator device","authors":"Francis Nikolai Lupena, Siew Mei Teo, Rowin V. Galarce","doi":"10.1109/IPFA.2016.7564273","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564273","url":null,"abstract":"There are recent failures on a Low Dropout (LDO) Regulator where the customer is experiencing an out of specification output voltage. This paper aims to investigate the exact root cause of the failure by detailed failure analysis and relating the customer complaint to the die crack observed.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"41 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114046582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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