Improvement of top-down delayering techniques on advanced technology nodes

2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI:10.1109/IPFA.2016.7564253

T. Hrncír, H. H. Yap, E. Moyal, J. Teshima

引用次数: 3

Abstract

An improved method of a planar IC sample delayering by FIB is proposed. The sample cleaving and FIB milling from two directions increases the quality of the delayered area. SEM allows accurate endpointing of the delayering on the layer of interest. The method allows to increase the delayered sample area significantly.

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先进技术节点自顶向下分层技术改进

提出了一种改进的基于FIB的平面集成电路样品分层方法。两个方向的试样切割和FIB铣削提高了延迟区质量。扫描电镜允许在感兴趣的层上精确地结束分层。该方法允许显著增加延迟样品面积。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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