G. Jan, L. Thomas, S. Le, Yuan-Jen Lee, Huanlong Liu, Jian Zhu, R. Tong, K. Pi, Yu-Jen Wang, D. Shen, R. He, J. Haq, J. Teng, V. Lam, R. Annapragada, T. Zhong, T. Torng, P. Wang
{"title":"Demonstration of an MgO based anti-fuse OTP design integrated with a fully functional STT-MRAM at the Mbit level","authors":"G. Jan, L. Thomas, S. Le, Yuan-Jen Lee, Huanlong Liu, Jian Zhu, R. Tong, K. Pi, Yu-Jen Wang, D. Shen, R. He, J. Haq, J. Teng, V. Lam, R. Annapragada, T. Zhong, T. Torng, P. Wang","doi":"10.1109/VLSIT.2015.7223663","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223663","url":null,"abstract":"STT-MRAM technology has been attracting renewed attention since the embedability of a working STT-MRAM design has been demonstrated [1]. In this paper we expand on the versatility of STT-MRAM by demonstrating the conversion of a standard STT-MRAM cell to a One Time Programmable (OTP) anti-fuse cell. Both designs are integrated at the Mbit level on a single chip using the same magnetic stack, processing and CMOS cell design. A single BEOL mask change can convert an STT-MRAM device to an OTP design by simply reducing its size. The increased resistance yields larger voltage drop across the device, due to the voltage divider effect in the 1T-1MTJ cell and is sufficient to trigger reliable dielectric breakdown of the oxide tunnel barrier, effectively shorting the device. In this paper we demonstrate the seamless integration of an OTP based on STT-MRAM and 100% programming and reading yield at the Mbit level.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132992539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Ragnarsson, H. Dekkers, T. Schram, S. Chew, B. Parvais, M. Dehan, K. Devriendt, Z. Tao, F. Sebaai, C. Baerts, S. Van Elshocht, N. Yoshida, A. Phatak, C. Lazik, A. Brand, W. Clark, D. Fried, D. Mocuta, K. Barla, N. Horiguchi, A. Thean
{"title":"RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs","authors":"L. Ragnarsson, H. Dekkers, T. Schram, S. Chew, B. Parvais, M. Dehan, K. Devriendt, Z. Tao, F. Sebaai, C. Baerts, S. Van Elshocht, N. Yoshida, A. Phatak, C. Lazik, A. Brand, W. Clark, D. Fried, D. Mocuta, K. Barla, N. Horiguchi, A. Thean","doi":"10.1109/VLSIT.2015.7223656","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223656","url":null,"abstract":"A novel RMG process in which the n-type work function metal (nWFM) is deposited first and then selectively removed from the pMOS devices is presented for the first time. The key benefit of this nMOS 1st process lies in increased gate-fill space which results in about 10× improvement in the pMOS effective gate resistivity at gate lengths (LG) around 22 nm, an improvement which is predicted by modeling to extend down to LG<;14 nm. The complete removal of the nWFM in the pMOS devices is evidenced by restored p-type effective work function (eWF) values in large area capacitors and matched pMOS threshold voltage (VT) values in bulk FinFET devices with LG down to 22 nm. Furthermore, selective removal of the nWFM is confirmed physically down to LG~16 nm providing further evidence that the process is scalable towards N7 dimensions.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130756868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Arun V. Thathachary, N. Agrawal, K. Bhuwalka, M. Cantoro, Yeon-Cheol Heo, G. Lavallee, S. Maeda, S. Datta
{"title":"Indium arsenide (InAs) single and dual quantum-well heterostructure FinFETs","authors":"Arun V. Thathachary, N. Agrawal, K. Bhuwalka, M. Cantoro, Yeon-Cheol Heo, G. Lavallee, S. Maeda, S. Datta","doi":"10.1109/VLSIT.2015.7223677","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223677","url":null,"abstract":"This work presents experimental demonstration of InAs single and dual quantum well (DQW) heterostructure FinFETs (FF) and their superior performance over In<sub>0.7</sub>Ga<sub>0.3</sub>As QW FF. Peak mobility of 3,531 cm<sup>2</sup>/V-sec and 3,950 cm<sup>2</sup>/V-sec are obtained for InAs single QW FF and InAs DQW FF, respectively, at a fin width (W<sub>fin</sub>) of 40nm and L<sub>G</sub> = 2μm. Peak g<sub>m</sub> of 480 μS/μm, 541 μS/um; I<sub>DSAT</sub> of 121 μA/μm, 135 μA/μm; and SS<sub>SAT</sub> of 101 mV/dec,103 mV/dec is demonstrated for single and DQW FF, respectively, at L<sub>G</sub>=300nm (V<sub>D</sub> = 0.5V, I<sub>OFF</sub>=100 nA/μm). Finally, InAs DQW is shown to be a viable alternate channel for high aspect ratio n-channel FinFET.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126841738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Then, L. Chow, S. Dasgupta, S. Gardner, M. Radosavljevic, V. Rao, S. Sung, G. Yang, R. Chau
{"title":"High-performance low-leakage enhancement-mode high-K dielectric GaN MOSHEMTs for energy-efficient, compact voltage regulators and RF power amplifiers for low-power mobile SoCs","authors":"H. Then, L. Chow, S. Dasgupta, S. Gardner, M. Radosavljevic, V. Rao, S. Sung, G. Yang, R. Chau","doi":"10.1109/VLSIT.2015.7223674","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223674","url":null,"abstract":"We have fabricated L<sub>G</sub>=90nm high-K dielectric enhancement-mode (e-mode) GaN MOS-HEMT which shows low I<sub>OFF</sub>=70nA/μm (V<sub>D</sub>=3.5V, V<sub>G</sub>=0V), low R<sub>ON</sub>=490Ω-μm, high I<sub>D,max</sub>=1.4mA/μm, and excellent power-added efficiency (PAE) of 80% at RF output power density (RF Pout) of 0.55W/mm (V<sub>D</sub>=3.5V, f=2.0GHz). These results represent (i) >3.6X lower RON at equivalent breakdown voltage (BV<sub>D</sub>) than industry-standard Si voltage regulator (VR) transistors, and (ii) >10% better PAE at matched RF Pout or >50% higher RF Pout at matched PAE than industry-standard GaAs RF power amplifier (PA) transistors, all at mobile SoC-compatible voltages. These results make GaN MOS-HEMTs attractive for realizing energy-efficient, compact voltage regulators and RF power amplifiers for mobile SoC. This work shows, for the first time, that the application space of GaN electronics can be expanded beyond the existing high-voltage power and RF electronics (e.g. automobile, power conversion, base-station, radar) to include low-power mobile SoCs.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129442082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Witters, J. Mitard, R. Loo, S. Demuynck, S. Chew, T. Schram, Z. Tao, A. Hikavyy, J. W. Sun, A. Milenin, H. Mertens, C. Vrancken, P. Favia, M. Schaekers, H. Bender, N. Horiguchi, R. Langer, K. Barla, D. Mocuta, N. Collaert, A. Thean
{"title":"Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect","authors":"L. Witters, J. Mitard, R. Loo, S. Demuynck, S. Chew, T. Schram, Z. Tao, A. Hikavyy, J. W. Sun, A. Milenin, H. Mertens, C. Vrancken, P. Favia, M. Schaekers, H. Bender, N. Horiguchi, R. Langer, K. Barla, D. Mocuta, N. Collaert, A. Thean","doi":"10.1109/VLSIT.2015.7223701","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223701","url":null,"abstract":"Strained Ge p-channel FinFETs on Strain Relaxed SiGe are integrated for the first time on high density 45nm Fin pitch using a replacement channel approach on Si substrate. In comparison to our previous work on isolated sGe FinFETs [1], 14/16nm technology node compatible modules such as replacement metal gate and germanide-free local interconnect were implemented. The ION/IOFF benchmark shows the high density strained Ge p-FinFETs in this work outperform the best published isolated strained Ge on SiGe devices.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129470332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"System challenges and hardware requirements for future consumer devices: From wearable to ChromeBooks and devices in-between","authors":"Eric Shiu, S. Prakash","doi":"10.1109/VLSIC.2015.7231378","DOIUrl":"https://doi.org/10.1109/VLSIC.2015.7231378","url":null,"abstract":"Internet and mobile application have been the driving force for semiconductor innovation in the past 10 years. In this paper, we will focus on the system requirement for today's and tomorrow's consumer gadgets from productivity laptop computers to wearable glasses or watches. We will start with everyone's favorite activity such as taking pictures and sharing with friends, listening to the YouTube music, having a Hangouts video chat, browsing the web for research or monitoring the fitness. We will break these activities into requirements for the software programmers, system architects, technologists and hardware engineers. The well-known memory and energy walls have been limiting the ever increasing compute horsepower and the performance perceived by the user. We will describe areas where hardware and software communities can work together to deliver the ultimate user satisfaction. Finally, a few future research areas in memory architecture, technology and circuit design will be discussed.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123941684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Tai, T. Ohyanagi, M. Kinoshita, T. Morikawa, K. Akita, M. Takato, H. Shirakawa, M. Araidai, K. Shiraishi, N. Takaura
{"title":"A 50-nm 1.2-V GexTe1−x/Sb2Te3 superlattice topological-switching random-access memory (TRAM)","authors":"M. Tai, T. Ohyanagi, M. Kinoshita, T. Morikawa, K. Akita, M. Takato, H. Shirakawa, M. Araidai, K. Shiraishi, N. Takaura","doi":"10.1109/VLSIT.2015.7223707","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223707","url":null,"abstract":"A 50nm topological-switching random-access memory (TRAM) was fabricated for the first time. A high-quality Ge<sub>x</sub>Te<sub>1-x</sub>/Sb<sub>2</sub>Te<sub>3</sub> superlattice film enabled set and reset voltages of TRAM to be less than 40% of those of PRAM. Statistical analysis of 16kb data showed the reset voltage to be less than 1.2 V, the lowest as a TRAM test chip.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"126 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120909972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Z. Ji, J. F. Zhang, L. Lin, M. Duan, W. Zhang, X. Zhang, R. Gao, B. Kaczer, J. Franco, T. Schram, N. Horiguchi, S. De Gendt, G. Groeseneken
{"title":"A test-proven As-grown-Generation (A-G) model for predicting NBTI under use-bias","authors":"Z. Ji, J. F. Zhang, L. Lin, M. Duan, W. Zhang, X. Zhang, R. Gao, B. Kaczer, J. Franco, T. Schram, N. Horiguchi, S. De Gendt, G. Groeseneken","doi":"10.1109/VLSIT.2015.7223693","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223693","url":null,"abstract":"For the first time, we demonstrate that A-G model extracted from short Vg-accelerated stresses can predict both long term DC and AC NBTI under low and dynamic operation Vg. This is achieved by successfully separating non-saturating defects from the saturating ones, allowing reliable extraction of power exponents needed for long term prediction. Unlike R-D model, A-G model does not require solving differential equations for AC NBTI. This saves computation time significantly, especially for high-frequency that needs small time-step, and makes it readily implementable in SPICE-like simulators.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132614461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Tien, N. Sturcken, Naigang Wang, J. Nah, B. Dang, E. O'Sullivan, P. Andry, M. Petracca, L. Carloni, W. Gallagher, K. Shepard
{"title":"An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors","authors":"K. Tien, N. Sturcken, Naigang Wang, J. Nah, B. Dang, E. O'Sullivan, P. Andry, M. Petracca, L. Carloni, W. Gallagher, K. Shepard","doi":"10.1109/VLSIT.2015.7223648","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223648","url":null,"abstract":"This paper presents a three-dimensional (3D) fully integrated high-speed multiphase voltage regulator. A complete switched-inductor regulator is integrated with a four-plane NoC in a two-high chip stack combining integrated magnetics, through-silicon vias (TSVs), and 45-nm SOI CMOS devices. Quasi-V2 hysteretic control is implemented over eight injection-locked fixed-frequency phases to achieve fast response, steady-state regulation, and fixed switching frequency. Peak efficiency of 82% for conversion from 1.66 V to 0.83 V is observed at a 150 MHz per-phase switching frequency. This is the first demonstration of high-speed voltage regulation using on-chip magnetic-core inductors in a 3D stack and achieves sub-μs dynamic supply voltage scaling for high-density embedded processing applications.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132029102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Huang, S. W. Chang, M. Chen, C. Fan, H. T. Lin, C. H. Lin, R. Chu, K. Y. Lee, M. A. Khaderbad, Z. Chen, C. H. Chen, L. T. Lin, H. Lin, H. Chang, C. Yang, Y. Leung, Y. Yeo, S. Jang, H. Hwang, Carlos H. Díaz
{"title":"In0.53Ga0.47As MOSFETs with high channel mobility and gate stack quality fabricated on 300 mm Si substrate","authors":"M. Huang, S. W. Chang, M. Chen, C. Fan, H. T. Lin, C. H. Lin, R. Chu, K. Y. Lee, M. A. Khaderbad, Z. Chen, C. H. Chen, L. T. Lin, H. Lin, H. Chang, C. Yang, Y. Leung, Y. Yeo, S. Jang, H. Hwang, Carlos H. Díaz","doi":"10.1109/VLSIT.2015.7223675","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223675","url":null,"abstract":"In<sub>0.53</sub>Ga<sub>0.47</sub>As channel MOSFETs were fabricated on 300 mm Si substrate. The epitaxial In<sub>0.53</sub>Ga<sub>0.47</sub>As channel layer exhibits high Hall electron mobility comparable to those grown on lattice matched InP substrates. Excellent device characteristics (SS~95 mV/dec., I<sub>on</sub>/I<sub>off</sub> ~10<sup>5</sup>, DIBL ~51 mV/V at V<sub>ds</sub> = 0.5V for L<sub>g</sub>=150 nm device) with good uniformity across the wafer were demonstrated. The extracted high field effect mobility (μ<sub>EF</sub> = 1837 cm<sup>2</sup>/V-s with EOT ~ 0.9 nm) is among the highest values reported for surface channel In<sub>0.53</sub>Ga<sub>0.47</sub>As MOSFETs.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125741310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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