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2015 Symposium on VLSI Technology (VLSI Technology)最新文献

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Ultra fine-pitch TSV technology for ultra-dense high-Q RF inductors 用于超高密度高q射频电感器的超细间距TSV技术
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-08-27 DOI: 10.1109/VLSIT.2015.7223700
W. Vitale, M. Fernandez-Bolaños, A. Klumpp, J. Weber, P. Ramm, A. Ionescu
{"title":"Ultra fine-pitch TSV technology for ultra-dense high-Q RF inductors","authors":"W. Vitale, M. Fernandez-Bolaños, A. Klumpp, J. Weber, P. Ramm, A. Ionescu","doi":"10.1109/VLSIT.2015.7223700","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223700","url":null,"abstract":"We demonstrate that fine-pitch TSV technology can be exploited to fabricate micro-inductors on high resistivity substrate, with record-high inductance per area and preserving their performance at GHz frequencies. We report an extensive experimental study on the effects of dimensional scaling and passive device density on RF performance of out-of-plane inductors exploiting W-based TSVs, with pitches down to 10 μm. We show wideband RF inductors with an unprecedented combination of a quality factor peak of 7.8 at 13 GHz, self-resonance frequency of 29.2 GHz, and inductance density of 124.4 nH/mm2. The reported technology also includes low loss interconnects, fixed capacitors and LC tanks, design to serving high performance 3D-integrated RF functionalities.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123827999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A novel dichotomic programming algorithm applied to 3D NAND flash 应用于三维NAND闪存的一种新的二分类编程算法
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223669
C. Hsieh, H. Lue, Yung-Chun Li, Ti-Wen Chen, Hsiang-Pang Li, Chih-Yuan Lu
{"title":"A novel dichotomic programming algorithm applied to 3D NAND flash","authors":"C. Hsieh, H. Lue, Yung-Chun Li, Ti-Wen Chen, Hsiang-Pang Li, Chih-Yuan Lu","doi":"10.1109/VLSIT.2015.7223669","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223669","url":null,"abstract":"We introduce a novel programming algorithm that is particularly suitable for 3D NAND. With larger design rules and charge trapping (CT) device 3D NAND is much less sensitive to interference therefore should not use elaborate and costly algorithms designed for scaled 2D NAND. By binary division of cell Vt into smaller groups the number of verification pulses can be reduced. For MLC/TLC which requires large number of verification this can reduce the program time substantially. The algorithm is applied to a VG 3D NAND, and program noise and RTN are carefully studied and their impacts incorporated. An optimized dichotomic ISPP method is designed and tight and efficient MLC/TLC programming demonstrated.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116992185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A new integration technology platform: Integrated fan-out wafer-level-packaging for mobile applications 一个新的集成技术平台:移动应用的集成扇出晶圆级封装
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223697
Douglas Yu
{"title":"A new integration technology platform: Integrated fan-out wafer-level-packaging for mobile applications","authors":"Douglas Yu","doi":"10.1109/VLSIT.2015.7223697","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223697","url":null,"abstract":"3D sub-system integration of logic and DRAM with TSV is desirable for wide memory bandwidth and reduced power for mobile applications. However, its manufacturing cost, along with testing and heat dissipation, remains to be outstanding issues. A new integration technology platform, InFO, is proposed to address it. In this paper, we compare three main 3D integration architectures: InFO_PoP, FC_PoP and 3DIC with TSV based on mobile product requirements, including system power- performance-profile (form factor), heat dissipation, memory bandwidth and production cycle-time along with cost. InFO not only best optimizes and achieves the requirements, but also more readily integrates partitioned-chips, which further impacts on the manufacturing of the logic/DRAM sub-system.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116755132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
Confined Epitaxial Lateral Overgrowth (CELO): A novel concept for scalable integration of CMOS-compatible InGaAs-on-insulator MOSFETs on large-area Si substrates 局限外延横向过度生长(CELO):在大面积Si衬底上可扩展集成cmos兼容InGaAs-on-insulator mosfet的新概念
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223666
L. Czornomaz, E. Uccelli, M. Sousa, V. Deshpande, V. Djara, D. Caimi, M. Rossell, R. Erni, J. Fompeyrine
{"title":"Confined Epitaxial Lateral Overgrowth (CELO): A novel concept for scalable integration of CMOS-compatible InGaAs-on-insulator MOSFETs on large-area Si substrates","authors":"L. Czornomaz, E. Uccelli, M. Sousa, V. Deshpande, V. Djara, D. Caimi, M. Rossell, R. Erni, J. Fompeyrine","doi":"10.1109/VLSIT.2015.7223666","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223666","url":null,"abstract":"We report on the first demonstration of the CMOS-compatible integration of high-quality InGaAs on insulator (InGaAs-OI) on Si substrates by a novel concept named Confined Epitaxial Lateral Overgrowth (CELO). This method, based on selective epitaxy, only requires the use of standard large-area silicon substrates and typical CMOS processes. It enables the fabrication of InGaAs-OI starting from both bulk and SOI Si wafers. The InGaAs epitaxial structures are characterized by a very low defectivity, and can fulfill the requirements of both ultra-thin-body and fins-based advanced CMOS nodes. Gate-first self-aligned FinFETs (100-nm-long gate, 50-nm-wide fins and 250-nm-wide plug-contacts) with excellent electrical characteristics comparable to start-of-the-art InGaAs MOSFETs on Si are demonstrated, highlighting that this new concept has significant potential to enable introduction of high-mobility channel materials in high-volume manufacturing of advanced CMOS nodes.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121454757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 76
Sub-μW standby power, <18 µW/DMIPS@25MHz MCU with embedded atom-switch programmable logic and ROM 亚μW待机功率，<18 μW /DMIPS@25MHz MCU，内置原子开关可编程逻辑和ROM
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223636
Y. Tsuji, X. Bai, M. Miyamura, T. Sakamoto, M. Tada, N. Banno, K. Okamoto, N. Iguchi, N. Sugii, H. Hada
{"title":"Sub-μW standby power, <18 µW/DMIPS@25MHz MCU with embedded atom-switch programmable logic and ROM","authors":"Y. Tsuji, X. Bai, M. Miyamura, T. Sakamoto, M. Tada, N. Banno, K. Okamoto, N. Iguchi, N. Sugii, H. Hada","doi":"10.1109/VLSIT.2015.7223636","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223636","url":null,"abstract":"A non-volatile programmable logic (NPL) with atom switch significantly accelerates performance of micro-controller unit. A low-power 32bit-CPU using a 65 nm-node Silicon-on-Thin-Box (SOTB) CMOS performs 1.95 DMIPS/MHz and 33 μW/MHz on 25 MHz and VDD=0.4V. When a software process in the CPU is offloaded to NPL, the 9 times faster processing speed and 3 times higher energy efficiency are realized. A reverse body-bias on SOTB CMOS and a power-off of NPL block suppress a standby power down to 0.7 μW.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133434325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS 栅极全能nwfet与三栅极finfet:用于多vt CMOS的可控EWF调制的无结、无扩展和传统结器件
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223652
A. Veloso, G. Hellings, M. Cho, E. Simoen, K. Devriendt, V. Paraschiv, E. Vecchio, Z. Tao, J. Versluijs, L. Souriau, H. Dekkers, S. Brus, J. Geypen, P. Lagrain, H. Bender, G. Eneman, P. Matagne, A. De Keersgieter, W. Fang, N. Collaert, A. Thean
{"title":"Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS","authors":"A. Veloso, G. Hellings, M. Cho, E. Simoen, K. Devriendt, V. Paraschiv, E. Vecchio, Z. Tao, J. Versluijs, L. Souriau, H. Dekkers, S. Brus, J. Geypen, P. Lagrain, H. Bender, G. Eneman, P. Matagne, A. De Keersgieter, W. Fang, N. Collaert, A. Thean","doi":"10.1109/VLSIT.2015.7223652","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223652","url":null,"abstract":"We report a comprehensive evaluation of different device architectures from a device and circuit performance viewpoint: gate-all-around (GAA) nanowire (NW) FETs vs. triple-gate finFETs, both built using various doping schemes. GAA devices are obtained via a fins release process, high density compatible, at replacement metal gate (RMG) module, and outperform others per footprint. Junctionless (JL) GAA-NWFETs with excellent electrostatics and smaller IOFF values yield ring oscillators (RO) with substantially lower power dissipation and considerably longer BTI lifetime. Improved reliability is also obtained for extensionless vs. reference FETs with conventional junctions, at comparable device and circuit performance. In addition, a TiAl-based EWF-metal is introduced for the first time in a GAA configuration resulting in higher performing, low-VT, n-type GAA-NWFETs and single-MG 6T-SRAM cells. Noise results show no significant impact of device architecture on gate stack integrity and some benefit for JL and TiAl-based GAA-NWFETs.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133631603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Technology innovation in an IoT era 物联网时代的技术创新
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223643
A. Steegen
{"title":"Technology innovation in an IoT era","authors":"A. Steegen","doi":"10.1109/VLSIT.2015.7223643","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223643","url":null,"abstract":"The further growth of billions of wirelessly connected devices requires a technology infrastructure that can handle a massive increase in storage, computing power and bandwidth, some of it available via cloud computing, to enable number crunching at very large scale and at high volume, low cost and low power. The IoT applications or `smart devices' require the following technology enablers: ultra-low power, integration of memory and processing power to drive context awareness, security, advanced communication using smart antennas and improved analog performance, compactness by co-integration or stacking of heterogeneous systems.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123643851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs 一种用于降低finfet寄生电容的新型ALD SiBCN低k间隔器
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223659
T. Yamashita, S. Mehta, V. Basker, R. Southwick, A. Kumar, R. Kambhampati, R. Sathiyanarayanan, J. Johnson, T. Hook, S. Cohen, J. Li, A. Madan, Z. Zhu, L. Tai, Y. Yao, P. Chinthamanipeta, M. Hopstaken, Z. Liu, D. Lu, F. Chen, S. Khan, D. Canaperi, B. Haran, J. Stathis, P. Oldiges, C. Lin, S. Narasimha, A. Bryant, W. Henson, S. Kanakasabapathy, K. Murali, T. Gow, D. Mcherron, H. Bu, M. Khare
{"title":"A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs","authors":"T. Yamashita, S. Mehta, V. Basker, R. Southwick, A. Kumar, R. Kambhampati, R. Sathiyanarayanan, J. Johnson, T. Hook, S. Cohen, J. Li, A. Madan, Z. Zhu, L. Tai, Y. Yao, P. Chinthamanipeta, M. Hopstaken, Z. Liu, D. Lu, F. Chen, S. Khan, D. Canaperi, B. Haran, J. Stathis, P. Oldiges, C. Lin, S. Narasimha, A. Bryant, W. Henson, S. Kanakasabapathy, K. Murali, T. Gow, D. Mcherron, H. Bu, M. Khare","doi":"10.1109/VLSIT.2015.7223659","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223659","url":null,"abstract":"FinFET has become the mainstream logic device architecture in recent technology nodes due to its superior electrostatic and leakage control [1,2,3,4]. However, parasitic capacitance has been a key performance detractor in 3D FinFETs. In this work, a novel low temperature ALD-based SiBCN material has been identified, with an optimized spacer RIE process developed to preserve the low-k value and provide compatibility with the down-stream processes. The material has been integrated into a manufacturable 14nm replacement-metal-gate (RMG) FinFET baseline with a demonstrated ~8% performance improvement in the RO delay with reliability meeting the technology requirement [4]. A guideline for spacer design consideration for 10nm node and beyond is also provided based on the comprehensive material properties and reliability evaluations.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129645640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 1016 endurance 低功耗1T DRAM/NVM多功能存储器，具有陡峭的60 mv / 10年以下操作，快速20 ns速度，以及85°c外推1016耐用性
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223671
Y. Chiu, Chun‐Hu Cheng, Chun-Yen Chang, Min-Hung Lee, H. Hsu, S. Yen
{"title":"Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 1016 endurance","authors":"Y. Chiu, Chun‐Hu Cheng, Chun-Yen Chang, Min-Hung Lee, H. Hsu, S. Yen","doi":"10.1109/VLSIT.2015.7223671","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223671","url":null,"abstract":"In this work, we report a one-transistor (1T) versatile memory; the memory transistor characteristics achieve sub-60-mV/dec operation and considerably low off-state leakage of 10<sup>-15</sup> A/μm at a supply voltage below 0.5V. The versatile memory features DRAM/NVM functions of large ΔV<sub>T</sub> window of 2.8V, fast 20-ns speed, 10<sup>3</sup>s retention at 85°C, and long extrapolated 10<sup>16</sup> endurance at 85°C, which show the potential for 3D memory application with severe requirement on both high density and low power consumption.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131327372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Vertical device architecture for 5nm and beyond: Device & circuit implications 5nm及以上的垂直器件架构:器件和电路的影响
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223689
A. Thean, D. Yakimets, T. Huynh Bao, P. Schuddinck, S. Sakhare, M. Bardon, A. Sibaja-Hernandez, I. Ciofi, G. Eneman, A. Veloso, J. Ryckaert, P. Raghavan, A. Mercha, A. Mocuta, Z. Tokei, D. Verkest, P. Wambacq, K. De Meyer, N. Collaert
{"title":"Vertical device architecture for 5nm and beyond: Device & circuit implications","authors":"A. Thean, D. Yakimets, T. Huynh Bao, P. Schuddinck, S. Sakhare, M. Bardon, A. Sibaja-Hernandez, I. Ciofi, G. Eneman, A. Veloso, J. Ryckaert, P. Raghavan, A. Mercha, A. Mocuta, Z. Tokei, D. Verkest, P. Wambacq, K. De Meyer, N. Collaert","doi":"10.1109/VLSIT.2015.7223689","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223689","url":null,"abstract":"Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125384687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
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