2015 Symposium on VLSI Technology (VLSI Technology)最新文献_第9页

Automated driving - Impacts on the vehicle architecture 自动驾驶——对车辆架构的影响

2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.2015.7231288

M. Fausten, Thorsten Huck, A. Ruhle, T. Baysal, R. Kornhaas

引用次数: 0

Design and demonstration of reliability-aware Ge gate stacks with 0.5 nm EOT 具有0.5 nm EOT的可靠性感知Ge栅极堆栈的设计与演示

2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.2015.7231383

C. Lu, C. H. Lee, T. Nishimura, A. Toriumi

引用次数: 6

Technology / circuits joint evening panel discussion semiconductor industry in 2020: Evolution or revolution? Tuesday, June 16, 20:00–22:00 2020年半导体产业:进化还是革命?6月16日，星期二，20:00-22:00

2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 1900-01-01 DOI: 10.1109/vlsit.2015.7223720

引用次数: 0

A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products 14纳米SoC平台技术，采用第二代三栅极晶体管、70纳米栅极间距、52纳米金属间距和0.0499 um2 SRAM单元，针对低功耗、高性能和高密度SoC产品进行了优化

2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 1900-01-01 DOI: 10.1109/vlsit.2015.7223683

C. Jan, F. Al-amoody, H. Chang, T. Chang, Y. Chen, N. Dias, W. Hafez, D. Ingerly, M. Jang, E. Karl, S. Shi, K. Komeyli, H. Kilambi, A. Kumar, K. Byon, C. Lee, J. Lee, T. Leo, P. Liu, N. Nidhi, R. Olac-vaw, C. Petersburg, K. Phoa, C. Prasad, C. Quincy, R. Ramaswamy, T. Rana, L. Rockford, A. Subramaniam, C. Tsai, P. Vandervoorn, L. Yang, A. Zainuddin, P. Bai

{"title":"A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products","authors":"C. Jan, F. Al-amoody, H. Chang, T. Chang, Y. Chen, N. Dias, W. Hafez, D. Ingerly, M. Jang, E. Karl, S. Shi, K. Komeyli, H. Kilambi, A. Kumar, K. Byon, C. Lee, J. Lee, T. Leo, P. Liu, N. Nidhi, R. Olac-vaw, C. Petersburg, K. Phoa, C. Prasad, C. Quincy, R. Ramaswamy, T. Rana, L. Rockford, A. Subramaniam, C. Tsai, P. Vandervoorn, L. Yang, A. Zainuddin, P. Bai","doi":"10.1109/vlsit.2015.7223683","DOIUrl":"https://doi.org/10.1109/vlsit.2015.7223683","url":null,"abstract":"A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um2 HDC SRAM cells are the most aggressive design rules reported for 14/16 nm node SoC process to achieve Moore's Law 2x density scaling over 22 nm node. High performance NMOS/PMOS drive currents of 1.3/1.2 mA/um, respectively, have been achieved at 0.7 V and 100 nA/um off-state leakage, 37%/50% improvement over 22 nm node. Ultra-low power NMOS/PMOS drives are 0.50/0.32 mA/um at 0.7 V and 15pA/um Ioff. This technology also deploys high voltage I/O transistors to support up to 3.3 V I/O. A full suite of analog, mixed-signal and RF features are also supported.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114561899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1