具有0.5 nm EOT的可靠性感知Ge栅极堆栈的设计与演示

2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 1900-01-01 DOI:10.1109/VLSIC.2015.7231383

C. Lu, C. H. Lee, T. Nishimura, A. Toriumi

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引用次数: 6

摘要

本文首次提出了一种基于材料/工艺的可靠性感知栅极堆叠设计方法。初期良好的栅极堆叠特性并不一定能保证器件的长期可靠性。为了克服这一巨大的障碍，我们研究了GeO2网络的稳定性以及新的高k的形成。证明了具有0.5 nm EOT和足够低Dit的非常稳健的Ge栅极堆栈。

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Design and demonstration of reliability-aware Ge gate stacks with 0.5 nm EOT

This paper reports a novel material/process-based design for reliability-aware Ge gate stack for the first time. Initially good characteristics of Ge gate stacks do not necessarily guarantee the long-term device reliability. To overcome the big hurdle, we have investigated the stability of GeO2 network as well as the formation of new high-k. The very robust Ge gate stack with both 0.5 nm EOT and sufficiently low Dit is demonstrated.

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2015 Symposium on VLSI Technology (VLSI Technology)

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