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2015 Symposium on VLSI Technology (VLSI Technology)最新文献

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Comprehensive analysis of retention characteristics in 3-D NAND flash memory cells with tube-type poly-Si channel structure 具有管型多晶硅沟道结构的三维NAND闪存单元保留特性的综合分析
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223670
Ho-Jung Kang, Nagyong Choi, S. Joe, Jihyun Seo, Eun-seok Choi, Sung-Kye Park, Byung-Gook Park, Jong-Ho Lee
{"title":"Comprehensive analysis of retention characteristics in 3-D NAND flash memory cells with tube-type poly-Si channel structure","authors":"Ho-Jung Kang, Nagyong Choi, S. Joe, Jihyun Seo, Eun-seok Choi, Sung-Kye Park, Byung-Gook Park, Jong-Ho Lee","doi":"10.1109/VLSIT.2015.7223670","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223670","url":null,"abstract":"Retention characteristics of a 3-D NAND flash cell with tube-type poly-Si body are investigated at a high temperature (T) depending on program (P), neutral (N), and erase (E) states of adjacent cells. The trap density (N<sub>t</sub>) in the nitride storage layer of the cell is extracted by utilizing retention model and deriving related equations in cylindrical coordinate. By programming or erasing adjacent cells, we can separate laterally distributed charge component from the retention characteristics. The adjacent cells which are programmed suppress significantly the lateral diffusion at a high T so that we can extract accurate N<sub>t</sub> profile. Extracted peak of N<sub>t</sub> at P-P-P mode is ~1.2×10<sup>19</sup> cm<sup>-3</sup>eV<sup>-1</sup> at an E<sub>C</sub>-E<sub>T</sub> of 1.0 eV. Retention characteristics with effective gate length and word-line biasing are also investigated.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121843801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Novel selector for high density non-volatile memory with ultra-low holding voltage and 107 on/off ratio 新颖的高密度非易失性存储器选择器，超低保持电压和107开/关比
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223716
Hongxin Yang, Minghua Li, W. He, Yu Jiang, K. Lim, Wendong Song, V. Y. Zhuo, C. C. Tan, E. Chua, Weijie Wang, Yi Yang, R. Ji
{"title":"Novel selector for high density non-volatile memory with ultra-low holding voltage and 107 on/off ratio","authors":"Hongxin Yang, Minghua Li, W. He, Yu Jiang, K. Lim, Wendong Song, V. Y. Zhuo, C. C. Tan, E. Chua, Weijie Wang, Yi Yang, R. Ji","doi":"10.1109/VLSIT.2015.7223716","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223716","url":null,"abstract":"We present a novel selector made of doped-chalcogenide material. This selector not only achieves low holding voltage (0.2 V) and large on/off ratio (>107), but also exhibits the high on-current density (>1.6 MA/cm2) and large hysteresis window (1.2 V). Besides, excellent selector performances with ultra-low off-state leakage current (10 pA), high switching speed (<;10 ns), high endurance (>109), good thermal stability (up to 180°C) have been demonstrated. Furthermore, the device exhibits good scalability which is suitable for 3D array integrations.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"65 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114004950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
Impact of random telegraph noise on write stability in Silicon-on-Thin-BOX (SOTB) SRAM cells at low supply voltage in sub-0.4V regime 随机电报噪声对SRAM电池在低于0.4 v低电压下写入稳定性的影响
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223694
Hao Qiu, T. Mizutani, Yoshiki Yamamoto, H. Makiyama, T. Yamashita, H. Oda, S. Kamohara, N. Sugii, T. Saraya, M. Kobayashi, T. Hiramoto
{"title":"Impact of random telegraph noise on write stability in Silicon-on-Thin-BOX (SOTB) SRAM cells at low supply voltage in sub-0.4V regime","authors":"Hao Qiu, T. Mizutani, Yoshiki Yamamoto, H. Makiyama, T. Yamashita, H. Oda, S. Kamohara, N. Sugii, T. Saraya, M. Kobayashi, T. Hiramoto","doi":"10.1109/VLSIT.2015.7223694","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223694","url":null,"abstract":"The effect of random telegraph noise (RTN) on write stability of SRAM cells in sub-0.4V operation is intensively measured and statistically analyzed. RTN of N-curves in Silicon-on-Thin-BOX (SOTB) cells is monitored. By developing statistical models, it is found that, different from bulk SRAM cells operating at high supply voltage (VDD), fail bit rate (FBR) at sub-0.4V is degraded by RTN. The origin of high FBR due to RTN at sub-0.4V is discussed.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122415526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A comparison of arsenic and phosphorus extension by Room Temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions 比较了N7 (7nm) NMOS Si块体finfet中与翅片尺寸相关的室温和热离子注入对砷磷的影响
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223691
Y. Sasaki, R. Ritzenthaler, A. De Keersgieter, T. Chiarella, S. Kubicek, E. Rosseel, A. Waite, J. I. del Agua Borniquel, B. Colombeau, S. Chew, M. Kim, T. Schram, S. Demuynck, W. Vandervorst, N. Horiguchi, D. Mocuta, A. Mocuta, A. Thean
{"title":"A comparison of arsenic and phosphorus extension by Room Temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions","authors":"Y. Sasaki, R. Ritzenthaler, A. De Keersgieter, T. Chiarella, S. Kubicek, E. Rosseel, A. Waite, J. I. del Agua Borniquel, B. Colombeau, S. Chew, M. Kim, T. Schram, S. Demuynck, W. Vandervorst, N. Horiguchi, D. Mocuta, A. Mocuta, A. Thean","doi":"10.1109/VLSIT.2015.7223691","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223691","url":null,"abstract":"We compare As and P extension implants for NMOS Si bulk FinFETs with 5nm wide fins. P implanted FinFETs shows improved ION, +15% with Room Temperature (RT) ion implantation (I/I) and +9% with hot I/I, keeping matched Short Channel Effects (SCE) for gate length (LG) of 30nm compared with As implanted FinFETs. Based on TCAD work, P increases activated dopant concentration in extension compared with As and 5nm fin suppresses off state leakage current under the gate efficiently even in P extension case though P diffusion is faster than As.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"63 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114111941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
First experimental demonstration of Ge 3D FinFET CMOS circuits Ge三维FinFET CMOS电路的首次实验演示
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223702
Heng Wu, Wei Luo, Hong Zhou, M. Si, Jingyun Zhang, P. Ye
{"title":"First experimental demonstration of Ge 3D FinFET CMOS circuits","authors":"Heng Wu, Wei Luo, Hong Zhou, M. Si, Jingyun Zhang, P. Ye","doi":"10.1109/VLSIT.2015.7223702","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223702","url":null,"abstract":"We report the first experimental demonstration of Ge 3D CMOS circuits, based on the recessed fin structure. Both n-FinFETs and p-FinFETs with channel length (Lch) from 200 to 20 nm and fin width (WFin) from 60 to 10 nm are realized on a Ge-on-insulator (GeOI) substrate. The Ge FinFETs show superior gate electrostatic control over planar devices and sub-threshold slope (SS) as low as 93 and 73 mV/dec are obtained on n- and p-FETs, respectively. Combining the n- and p- type 3D devices together, the FinFET CMOS inverters have high voltage gain up to 34 V/V at VDD of 1.4 V, delivering more than 200% improvement over the planar ones at the same Lch of 200 nm. Scalability studies are also carried out for both types of FinFETs in terms of Lch and WFin.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122873066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
30-nm-channel-length c-axis aligned crystalline In-Ga-Zn-O transistors with low off-state leakage current and steep subthreshold characteristics 30纳米通道长度的c轴排列晶体In-Ga-Zn-O晶体管，具有低的断开状态泄漏电流和陡峭的亚阈值特性
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223680
S. Matsuda, T. Hiramatsu, R. Honda, D. Matsubayashi, H. Tomisu, Y. Kobayashi, K. Tochibayashi, R. Hodo, H. Fujiki, Y. Yamamoto, M. Tsubuku, Y. Okazaki, S. Yamazaki
{"title":"30-nm-channel-length c-axis aligned crystalline In-Ga-Zn-O transistors with low off-state leakage current and steep subthreshold characteristics","authors":"S. Matsuda, T. Hiramatsu, R. Honda, D. Matsubayashi, H. Tomisu, Y. Kobayashi, K. Tochibayashi, R. Hodo, H. Fujiki, Y. Yamamoto, M. Tsubuku, Y. Okazaki, S. Yamazaki","doi":"10.1109/VLSIT.2015.7223680","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223680","url":null,"abstract":"We report the world's smallest field effect transistors (FETs) with channel lengths of 32 nm including c-axis aligned crystalline (CAAC) In-Ga-Zn-O as their active layers, which achieve low off-state leakage currents. Furthermore, these FETs exhibit excellent subthreshold swing values despite having thick gate insulating film. The FET operation has been achieved owing to the 3D gate structure with a thin active layer, due to the FETs being accumulation-type FETs with intrinsic channels, and due to the dielectric anisotropy of the CAAC crystal structure.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121454566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Characterization of self-heating in high-mobility Ge FinFET pMOS devices 高迁移率Ge FinFET pMOS器件的自热特性
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223703
E. Bury, B. Kaczer, J. Mitard, N. Collaert, N. S. Khatami, Z. Akšamija, D. Vasileska, K. Raleva, L. Witters, G. Hellings, D. Linten, G. Groeseneken, A. Thean
{"title":"Characterization of self-heating in high-mobility Ge FinFET pMOS devices","authors":"E. Bury, B. Kaczer, J. Mitard, N. Collaert, N. S. Khatami, Z. Akšamija, D. Vasileska, K. Raleva, L. Witters, G. Hellings, D. Linten, G. Groeseneken, A. Thean","doi":"10.1109/VLSIT.2015.7223703","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223703","url":null,"abstract":"Based on physically-extended methodology, measurements and simulations show that implementing high-mobility materials and particularly alloys, such as a SiGe buffer for mobility enhancement in a Ge channel, can result in a 115% increase in self heating in the N7 node, compared to standard Si FinFETs.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120951079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Variation-tolerant dense TFET memory with low VMIN matching low-voltage TFET logic 具有低VMIN匹配低电压TFET逻辑的容差密度TFET存储器
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223688
D. Morris, U. Avci, I. Young
{"title":"Variation-tolerant dense TFET memory with low VMIN matching low-voltage TFET logic","authors":"D. Morris, U. Avci, I. Young","doi":"10.1109/VLSIT.2015.7223688","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223688","url":null,"abstract":"The tunneling FET (TFET) is a leading option for energy efficient computation with peak logic performance/watt greater than CMOS. With variation effects, TFET reaches 2X higher peak efficiency than MOSFET by using supply voltages under 0.4V. Dense TFET SRAM bitcell is proposed with VMIN matching this low logic VDD. Projections of device variation enable a comparison of TFET and MOSFET logic and memory and show greater robustness for TFET circuits. TFET bitcell write-time tracks logic frequency at low voltage. TFET bitcell retention margins are 0.1 V greater than that of the MOSFET. Bitcell performance and VMIN are improved by using TFET's unique asymmetric conduction to reduce write-contention and read-disturb conditions. A novel 7T bitcell with compact layout is proposed for improved low-voltage write.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129153202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A-VMCO: A novel forming-free, self-rectifying, analog memory cell with low-current operation, nonfilamentary switching and excellent variability A- vmco:一种新颖的无形成、自整流、模拟存储单元，具有低电流操作、非丝状开关和优异的可变性
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223717
B. Govoreanu, D. Crotti, S. Subhechha, Leqi Zhang, Y. Chen, S. Clima, Vasile Paraschiv, H. Hody, Christoph Adelmann, M. Popovici, O. Richard, Malgorzata Jurczak
{"title":"A-VMCO: A novel forming-free, self-rectifying, analog memory cell with low-current operation, nonfilamentary switching and excellent variability","authors":"B. Govoreanu, D. Crotti, S. Subhechha, Leqi Zhang, Y. Chen, S. Clima, Vasile Paraschiv, H. Hody, Christoph Adelmann, M. Popovici, O. Richard, Malgorzata Jurczak","doi":"10.1109/VLSIT.2015.7223717","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223717","url":null,"abstract":"We demonstrate a self-rectifying, compliance-free, BEOL CMOS-compatible, resistive switching memory device, with nonfilamentary switching mechanism, forming-free operation, analog switching behavior and excellent device to device operation uniformity, down to the smallest device size. The cells have a reset switching current density of ~0.3MA/cm2 (and ~10× lower set current). This corresponds to ~5uA reset current in a 40nm-size cell, projecting down to 1uA for a 20nm-size. The switching currents are tunable by process and structural cell design. The cells can be operated with pulses as short as 10ns, at below ±7V. Cycling for at least 106cy and retention of 55°C/3yr are demonstrated, with clear paths for further improvement. These key features are enabled by the use of an amorphous-Silicon (a-Si) barrier layer, which acts as a semi-insulating oxygen scavenger in a dual-layer a-Si/TiO2 active stack, being able to provide nonlinear IV cell characteristics, as well as to induce a large oxygen vacancy density in the switching layer.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131446444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Challenges for high-density 16Gb ReRAM with 27nm technology 采用27nm技术的高密度16Gb ReRAM面临的挑战
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIC.2015.7231366
S. Sills, Shuichiro Yasuda, A. Calderoni, Christopher Cardon, Jonathan Strand, K. Aratani, N. Ramaswamy
{"title":"Challenges for high-density 16Gb ReRAM with 27nm technology","authors":"S. Sills, Shuichiro Yasuda, A. Calderoni, Christopher Cardon, Jonathan Strand, K. Aratani, N. Ramaswamy","doi":"10.1109/VLSIC.2015.7231366","DOIUrl":"https://doi.org/10.1109/VLSIC.2015.7231366","url":null,"abstract":"Enabling a high-density ReRAM product requires: developing a cell that meets a stringent bit error rate, BER, at low program current, integrating the cell without material damage, and providing a high-drive selector at scaled nodes. We discuss ReRAM performance under these constraints and present a 16Gb, 27nm ReRAM capable of 105 cycles with BER <; 7×10-5.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131980837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
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