采用27nm技术的高密度16Gb ReRAM面临的挑战

2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI:10.1109/VLSIC.2015.7231366

S. Sills, Shuichiro Yasuda, A. Calderoni, Christopher Cardon, Jonathan Strand, K. Aratani, N. Ramaswamy

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引用次数: 22

摘要

实现高密度ReRAM产品需要:在低程序电流下开发符合严格误码率(BER)的单元，在不损坏材料的情况下集成单元，并在缩放节点上提供高驱动器选择器。我们在这些约束下讨论了ReRAM的性能，并提出了一个16Gb, 27nm的ReRAM，具有105个周期，BER <;7×纯。

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Challenges for high-density 16Gb ReRAM with 27nm technology

Enabling a high-density ReRAM product requires: developing a cell that meets a stringent bit error rate, BER, at low program current, integrating the cell without material damage, and providing a high-drive selector at scaled nodes. We discuss ReRAM performance under these constraints and present a 16Gb, 27nm ReRAM capable of 105 cycles with BER <; 7×10-5.

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2015 Symposium on VLSI Technology (VLSI Technology)

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