A comparison of arsenic and phosphorus extension by Room Temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions
Y. Sasaki, R. Ritzenthaler, A. De Keersgieter, T. Chiarella, S. Kubicek, E. Rosseel, A. Waite, J. I. del Agua Borniquel, B. Colombeau, S. Chew, M. Kim, T. Schram, S. Demuynck, W. Vandervorst, N. Horiguchi, D. Mocuta, A. Mocuta, A. Thean
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引用次数: 8
Abstract
We compare As and P extension implants for NMOS Si bulk FinFETs with 5nm wide fins. P implanted FinFETs shows improved ION, +15% with Room Temperature (RT) ion implantation (I/I) and +9% with hot I/I, keeping matched Short Channel Effects (SCE) for gate length (LG) of 30nm compared with As implanted FinFETs. Based on TCAD work, P increases activated dopant concentration in extension compared with As and 5nm fin suppresses off state leakage current under the gate efficiently even in P extension case though P diffusion is faster than As.
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