Variation-tolerant dense TFET memory with low VMIN matching low-voltage TFET logic

Abstract

The tunneling FET (TFET) is a leading option for energy efficient computation with peak logic performance/watt greater than CMOS. With variation effects, TFET reaches 2X higher peak efficiency than MOSFET by using supply voltages under 0.4V. Dense TFET SRAM bitcell is proposed with VMIN matching this low logic VDD. Projections of device variation enable a comparison of TFET and MOSFET logic and memory and show greater robustness for TFET circuits. TFET bitcell write-time tracks logic frequency at low voltage. TFET bitcell retention margins are 0.1 V greater than that of the MOSFET. Bitcell performance and VMIN are improved by using TFET's unique asymmetric conduction to reduce write-contention and read-disturb conditions. A novel 7T bitcell with compact layout is proposed for improved low-voltage write.