发布求助
文献互助 智能选刊 最新文献

2015 Symposium on VLSI Technology (VLSI Technology)最新文献

筛选
英文 中文
Considerations for efficient contact resistivity reduction via Fermi Level depinning - impact of MIS contacts on 10nm node nMOSFET DC characteristics 通过费米能级沉降有效降低接触电阻率的考虑——MIS触点对10nm节点nMOSFET直流特性的影响
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223710
J. Borrel, L. Hutin, O. Rozeau, P. Batude, T. Poiroux, F. Nemouchi, M. Vinet
{"title":"Considerations for efficient contact resistivity reduction via Fermi Level depinning - impact of MIS contacts on 10nm node nMOSFET DC characteristics","authors":"J. Borrel, L. Hutin, O. Rozeau, P. Batude, T. Poiroux, F. Nemouchi, M. Vinet","doi":"10.1109/VLSIT.2015.7223710","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223710","url":null,"abstract":"In the overwhelming majority of cases, current-voltage characteristics of metal-based contacts on semiconductors are non-linear around 0V even for degenerate interfacial doping levels. Any contact resistivity specification is therefore meaningless without the knowledge of the effective bias across the contact. For the first time, the efficiency of a dielectric insertion for contact resistance reduction was properly evaluated by solving the self-consistent case of voltage sharing for an aggressively scaled transistor flanked by two trench Metal/ Insulator/Semiconductor (MIS) contacts. We found that leveraging the Fermi Level depinning via optimized MIS contacts could lead to a +92% drive current (VGS=Vdd=0.7V) increase versus a Titanium liner-based silicidation-free approach.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"540 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127648565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Improved electromigration-resistance of Cu interconnects by graphene-based capping layer 石墨烯基封盖层提高铜互连的电迁移电阻
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223714
Seong Jun Yoon, A. Yoon, W. Hwang, Sung‐Yool Choi, B. Cho
{"title":"Improved electromigration-resistance of Cu interconnects by graphene-based capping layer","authors":"Seong Jun Yoon, A. Yoon, W. Hwang, Sung‐Yool Choi, B. Cho","doi":"10.1109/VLSIT.2015.7223714","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223714","url":null,"abstract":"We demonstrated that reduced graphene oxide (rGO) can suppress electromigration (EM) of Cu interconnect lines. This improvement in the EM lifetime is attributed to the presence of functional groups between the rGO and Cu atoms. Further enhancement of the EM lifetime was achieved by increasing the functionality of graphene by mixing graphene oxide (GO) with polyvinylpyrrolidone (PVP). It is revealed that the dominant EM path of Cu is successfully changed from the surface to grain boundaries by the use of an ultrathin (2.5 nm) PVP/GO capping layer.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121394697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Silicon-compatible low resistance S/D technologies for high-performance top-gate self-aligned InGaZnO TFTs with UTBB (ultra-thin body and BOX) structures 具有UTBB(超薄机身和BOX)结构的高性能顶栅自对准InGaZnO tft的硅兼容低电阻S/D技术
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223679
K. Ota, T. Irisawa, K. Sakuma, C. Tanaka, K. Ikeda, T. Tezuka, D. Matsushita, M. Saitoh
{"title":"Silicon-compatible low resistance S/D technologies for high-performance top-gate self-aligned InGaZnO TFTs with UTBB (ultra-thin body and BOX) structures","authors":"K. Ota, T. Irisawa, K. Sakuma, C. Tanaka, K. Ikeda, T. Tezuka, D. Matsushita, M. Saitoh","doi":"10.1109/VLSIT.2015.7223679","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223679","url":null,"abstract":"We have fabricated high-performance self-aligned top-gate InGaZnO TFTs with novel silicon-like source and drain (S/D) parasitic resistance (RSD) reduction processes. Ar ion implantation (Ar I/I) formed S/D extension layers and reduced RSD by inducing high-density carriers. First demonstration of self-aligned S/D metallization processes on InGaZnO surface (In-Ti alloy formation), just like silicidation, realized further RSD reduction. In addition, threshold voltage (Vth) controllability by back-gate bias was enhanced by adopting thin InGaZnO body and BOX. Successful applications of these booster technologies developed for Si LSIs enable us to fabricate high-performance top-gate scaled InGaZnO TFT in 3D LSI.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115894307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High sigma measurement of random threshold voltage variation in 14nm Logic FinFET technology 14nm逻辑FinFET技术中随机阈值电压变化的高sigma测量
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223657
M. Giles, N. Arkali Radhakrishna, D. Becher, A. Kornfeld, K. Maurice, S. Mudanai, S. Natarajan, P. Newman, P. Packan, T. Rakshit
{"title":"High sigma measurement of random threshold voltage variation in 14nm Logic FinFET technology","authors":"M. Giles, N. Arkali Radhakrishna, D. Becher, A. Kornfeld, K. Maurice, S. Mudanai, S. Natarajan, P. Newman, P. Packan, T. Rakshit","doi":"10.1109/VLSIT.2015.7223657","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223657","url":null,"abstract":"Random variation of threshold voltage (Vt) in MOSFETs plays a central role in determining the minimum operating voltage of products in a given process technology. Properly characterizing Vt variation requires a large volume of measurements of minimum size devices to understand the high sigma behavior. At the same time, a rapid measurement approach is required to keep the total measurement time practical. Here we describe a new test structure and measurement approach that enables practical characterization of Vt distributions to high sigma and its application to 14nm Logic FinFET technology. We show that both NMOS and PMOS single fin devices have very low random Vt variation of 19mV and 24mV respectively, normally distributed out to +/-5σ.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126950533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Novel oxygen showering process (OSP) for extreme damage suppression of sub-20nm high density p-MTJ array without IBE treatment 新型氧淋浴工艺(OSP)用于抑制亚20nm高密度p-MTJ阵列的极端损伤，无需IBE处理
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223660
J. Jeong, T. Endoh
{"title":"Novel oxygen showering process (OSP) for extreme damage suppression of sub-20nm high density p-MTJ array without IBE treatment","authors":"J. Jeong, T. Endoh","doi":"10.1109/VLSIT.2015.7223660","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223660","url":null,"abstract":"A novel damage recovery scheme using the oxygen showering post-treatment (OSP) is proposed to recover patterning damages and to improve electric and magnetic properties of p-MTJs, and its array yield. By applying our OSP to 25nm p-MTJs cell array, the MR was increased from 99% to 116% and the Isw was decreased from 41.1uA to 28.7uA. Moreover, electric short fails of MTJs array due to metallic by-products reduced dramatically by the selective oxidation of the damaged layer and its isolation from damage-less area. The OSP process makes the switching efficiency of 25nm patterned MTJs to be improved more than 30% compared with IBE treatment process. The mechanism of this enhancement is that spin directions of damaged area is changed from perpendicular to in-plane and, by this change, the energy barrier of damaged area is reduced. By the OSP treatment, we could develop the robust patterning process for sub-20nm STT-MRAM.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126955349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High hole mobility front-gate InAs/InGaSb-OI single structure CMOS on Si 高空穴迁移率前门InAs/InGaSb-OI单结构硅基CMOS
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223667
K. Nishi, M. Yokoyama, H. Yokoyama, T. Hoshi, H. Sugiyama, M. Takenaka, S. Takagi
{"title":"High hole mobility front-gate InAs/InGaSb-OI single structure CMOS on Si","authors":"K. Nishi, M. Yokoyama, H. Yokoyama, T. Hoshi, H. Sugiyama, M. Takenaka, S. Takagi","doi":"10.1109/VLSIT.2015.7223667","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223667","url":null,"abstract":"We have demonstrated the front-gate (FG) III-V single structure CMOS using ultra-thin body (UTB) InAs/InGaSb on insulator (-OI) on Si substrates with high hole mobility (μ<sub>eff</sub>) of 240 cm<sup>2</sup>V<sup>-1</sup>s<sup>-1</sup>. We have found that the μ<sub>eff</sub> is enhanced by the buffered-HF (BHF)-cleaned InAs MOS interfaces, Ni alloy S/D, and the InAs/strained InGaSb-OI hetero-interface channel. The CMOS operation using FG InAs/InGaSb-OI n/p-MOSFETs has been realized.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124950189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic 用于超低功耗逻辑的p型In0.7Ga0.3As/GaAs0.35Sb0.65和n型GaAs0.4Sb0.6/In0.65Ga0.35As互补异质结垂直隧道场效应管的演示
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223676
R. Pandey, H. Madan, H. Liu, V. Chobpattana, M. Barth, B. Rajamohanan, M. Hollander, T. Clark, K. Wang, J-H Kim, D. Gundlach, K. Cheung, J. Suehle, R. Engel-Herbert, S. Stemmer, S. Datta
{"title":"Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic","authors":"R. Pandey, H. Madan, H. Liu, V. Chobpattana, M. Barth, B. Rajamohanan, M. Hollander, T. Clark, K. Wang, J-H Kim, D. Gundlach, K. Cheung, J. Suehle, R. Engel-Herbert, S. Stemmer, S. Datta","doi":"10.1109/VLSIT.2015.7223676","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223676","url":null,"abstract":"Extremely scaled high-k gate dielectrics with high quality electrical interfaces with arsenide (As) and antimonide (Sb) channels are used to demonstrate complimentary `all III-V' Heterojunction Vertical Tunnel FET (HVTFET) with record performance at |V<sub>DS</sub>|=0.5V. The p-type TFET (PTFET) has I<sub>ON</sub> =30μA/μm and I<sub>ON</sub>/I<sub>OFF</sub> =10<sup>5</sup>, whereas the n-type TFET (NTFET) has I<sub>ON</sub> =275μA/μm and I<sub>ON</sub>/I<sub>OFF</sub>=3×10<sup>5</sup>, respectively. NTFET shows 55mV/decade switching slope (SS) while PTFET shows 115mV/decade SS in pulsed mode measurement. Vertical TFET offers 77% higher effective drive strength than Si-FinFET for given inverter standard cell area. Energy-delay performance of TFET shows gain over CMOS for low V<sub>DD</sub> logic applications.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130732172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Operation fundamentals in 12Mb Phase Change Memory based on innovative Ge-rich GST materials featuring high reliability performance 基于创新富ge GST材料的12Mb相变存储器的操作基础，具有高可靠性性能
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223708
V. Sousa, G. Navarro, N. Castellani, M. Coue, O. Cueto, C. Sabbione, P. Noé, L. Perniola, S. Blonkowski, P. Zuliani, R. Annunziata
{"title":"Operation fundamentals in 12Mb Phase Change Memory based on innovative Ge-rich GST materials featuring high reliability performance","authors":"V. Sousa, G. Navarro, N. Castellani, M. Coue, O. Cueto, C. Sabbione, P. Noé, L. Perniola, S. Blonkowski, P. Zuliani, R. Annunziata","doi":"10.1109/VLSIT.2015.7223708","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223708","url":null,"abstract":"For the first time, we present a Phase Change Memory (PCM) device with an optimized Ge-rich GeSbTe (GST) alloy integrated on a 12Mb test vehicle. We confirm that PCM can guarantee high data retention in extended temperature range and we provide the understanding of the high thermal stability of the two programmed states. We show how the elemental distribution reaches an equilibrium at the core of the storage element after the electrical activation of the cell, which relates to the strong opposition against crystallization of the RESET state. We also highlight the low number of grain boundaries along the conductive path of the optimized SET state, thus explaining the low drift of the resistance. Simulation results account for the experimental observations, showing how the segregation phenomena and the localization of the electronic switching impact the elemental distribution and the formation of the crystalline structure during programming.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132387269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
An 8-bit Analog-to-Digital Converter based on the voltage-dependent switching probability of a Magnetic Tunnel Junction 基于磁隧道结电压相关开关概率的8位模数转换器
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223662
W. Choi, Yang Lv, Hoonki Kim, Jianping Wang, C. Kim
{"title":"An 8-bit Analog-to-Digital Converter based on the voltage-dependent switching probability of a Magnetic Tunnel Junction","authors":"W. Choi, Yang Lv, Hoonki Kim, Jianping Wang, C. Kim","doi":"10.1109/VLSIT.2015.7223662","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223662","url":null,"abstract":"In this work, we have experimentally demonstrated for the first time, an Analog-to-Digital Converter (ADC) based on the unique voltage-dependent switching probability of a Magnetic Tunnel Junction (MTJ). The switching probability was calculated by applying repetitive voltage pulses and measuring the resolved MTJ states in each sampling time window. Temperature sensitivity and MgO breakdown issues were minimized by optimizing the voltage pulse width. Circuit level techniques were utilized to improve the ADC linearity and increase the input voltage range. The proposed ADC achieves an 8-bit resolution with excellent linearity at 30 and 85°C.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130278396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Self-limited RRAM with ON/OFF resistance ratio amplification 具有开/关电阻比放大的自限RRAM
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223715
S. Jo, T. Kumar, C. Zitlaw, H. Nazarian
{"title":"Self-limited RRAM with ON/OFF resistance ratio amplification","authors":"S. Jo, T. Kumar, C. Zitlaw, H. Nazarian","doi":"10.1109/VLSIT.2015.7223715","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223715","url":null,"abstract":"We demonstrate sub-5nm filament based electrochemical metallization RRAM with self-limited program in a reliable and controllable manner. This RRAM removes the necessity for any external current compliance in a 1TnR (1S1R) architecture. Furthermore, we report a novel technique to amplify RRAM's intrinsic ON/OFF resistance ratio by a factor of >104, which offers significant cell-, circuit- and system-level benefits such as reduced power, reduced BER and increased read bandwidth in high density RRAM.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116167166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信