Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic
R. Pandey, H. Madan, H. Liu, V. Chobpattana, M. Barth, B. Rajamohanan, M. Hollander, T. Clark, K. Wang, J-H Kim, D. Gundlach, K. Cheung, J. Suehle, R. Engel-Herbert, S. Stemmer, S. Datta
{"title":"Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic","authors":"R. Pandey, H. Madan, H. Liu, V. Chobpattana, M. Barth, B. Rajamohanan, M. Hollander, T. Clark, K. Wang, J-H Kim, D. Gundlach, K. Cheung, J. Suehle, R. Engel-Herbert, S. Stemmer, S. Datta","doi":"10.1109/VLSIT.2015.7223676","DOIUrl":null,"url":null,"abstract":"Extremely scaled high-k gate dielectrics with high quality electrical interfaces with arsenide (As) and antimonide (Sb) channels are used to demonstrate complimentary `all III-V' Heterojunction Vertical Tunnel FET (HVTFET) with record performance at |V<sub>DS</sub>|=0.5V. The p-type TFET (PTFET) has I<sub>ON</sub> =30μA/μm and I<sub>ON</sub>/I<sub>OFF</sub> =10<sup>5</sup>, whereas the n-type TFET (NTFET) has I<sub>ON</sub> =275μA/μm and I<sub>ON</sub>/I<sub>OFF</sub>=3×10<sup>5</sup>, respectively. NTFET shows 55mV/decade switching slope (SS) while PTFET shows 115mV/decade SS in pulsed mode measurement. Vertical TFET offers 77% higher effective drive strength than Si-FinFET for given inverter standard cell area. Energy-delay performance of TFET shows gain over CMOS for low V<sub>DD</sub> logic applications.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"38","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Symposium on VLSI Technology (VLSI Technology)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2015.7223676","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 38
Abstract
Extremely scaled high-k gate dielectrics with high quality electrical interfaces with arsenide (As) and antimonide (Sb) channels are used to demonstrate complimentary `all III-V' Heterojunction Vertical Tunnel FET (HVTFET) with record performance at |VDS|=0.5V. The p-type TFET (PTFET) has ION =30μA/μm and ION/IOFF =105, whereas the n-type TFET (NTFET) has ION =275μA/μm and ION/IOFF=3×105, respectively. NTFET shows 55mV/decade switching slope (SS) while PTFET shows 115mV/decade SS in pulsed mode measurement. Vertical TFET offers 77% higher effective drive strength than Si-FinFET for given inverter standard cell area. Energy-delay performance of TFET shows gain over CMOS for low VDD logic applications.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
