具有UTBB(超薄机身和BOX)结构的高性能顶栅自对准InGaZnO tft的硅兼容低电阻S/D技术

2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI:10.1109/VLSIT.2015.7223679

K. Ota, T. Irisawa, K. Sakuma, C. Tanaka, K. Ikeda, T. Tezuka, D. Matsushita, M. Saitoh

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引用次数: 4

摘要

我们制造了高性能的自对准顶栅InGaZnO tft，具有新颖的类硅源和漏极(S/D)寄生电阻(RSD)降低工艺。Ar离子注入(Ar I/I)通过诱导高密度载流子形成S/D扩展层，降低RSD。首次在InGaZnO表面展示了自对准S/D金属化工艺(In-Ti合金形成)，就像硅化一样，进一步降低了RSD。此外，采用薄InGaZnO本体和BOX增强了后门偏置阈值电压(Vth)的可控性。这些为Si LSI开发的升压技术的成功应用使我们能够在3D LSI中制造高性能顶栅缩放InGaZnO TFT。

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Silicon-compatible low resistance S/D technologies for high-performance top-gate self-aligned InGaZnO TFTs with UTBB (ultra-thin body and BOX) structures

We have fabricated high-performance self-aligned top-gate InGaZnO TFTs with novel silicon-like source and drain (S/D) parasitic resistance (RSD) reduction processes. Ar ion implantation (Ar I/I) formed S/D extension layers and reduced RSD by inducing high-density carriers. First demonstration of self-aligned S/D metallization processes on InGaZnO surface (In-Ti alloy formation), just like silicidation, realized further RSD reduction. In addition, threshold voltage (Vth) controllability by back-gate bias was enhanced by adopting thin InGaZnO body and BOX. Successful applications of these booster technologies developed for Si LSIs enable us to fabricate high-performance top-gate scaled InGaZnO TFT in 3D LSI.

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2015 Symposium on VLSI Technology (VLSI Technology)

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