J. Borrel, L. Hutin, O. Rozeau, P. Batude, T. Poiroux, F. Nemouchi, M. Vinet
{"title":"通过费米能级沉降有效降低接触电阻率的考虑——MIS触点对10nm节点nMOSFET直流特性的影响","authors":"J. Borrel, L. Hutin, O. Rozeau, P. Batude, T. Poiroux, F. Nemouchi, M. Vinet","doi":"10.1109/VLSIT.2015.7223710","DOIUrl":null,"url":null,"abstract":"In the overwhelming majority of cases, current-voltage characteristics of metal-based contacts on semiconductors are non-linear around 0V even for degenerate interfacial doping levels. Any contact resistivity specification is therefore meaningless without the knowledge of the effective bias across the contact. For the first time, the efficiency of a dielectric insertion for contact resistance reduction was properly evaluated by solving the self-consistent case of voltage sharing for an aggressively scaled transistor flanked by two trench Metal/ Insulator/Semiconductor (MIS) contacts. We found that leveraging the Fermi Level depinning via optimized MIS contacts could lead to a +92% drive current (VGS=Vdd=0.7V) increase versus a Titanium liner-based silicidation-free approach.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"540 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Considerations for efficient contact resistivity reduction via Fermi Level depinning - impact of MIS contacts on 10nm node nMOSFET DC characteristics\",\"authors\":\"J. Borrel, L. Hutin, O. Rozeau, P. Batude, T. Poiroux, F. Nemouchi, M. Vinet\",\"doi\":\"10.1109/VLSIT.2015.7223710\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In the overwhelming majority of cases, current-voltage characteristics of metal-based contacts on semiconductors are non-linear around 0V even for degenerate interfacial doping levels. Any contact resistivity specification is therefore meaningless without the knowledge of the effective bias across the contact. For the first time, the efficiency of a dielectric insertion for contact resistance reduction was properly evaluated by solving the self-consistent case of voltage sharing for an aggressively scaled transistor flanked by two trench Metal/ Insulator/Semiconductor (MIS) contacts. We found that leveraging the Fermi Level depinning via optimized MIS contacts could lead to a +92% drive current (VGS=Vdd=0.7V) increase versus a Titanium liner-based silicidation-free approach.\",\"PeriodicalId\":181654,\"journal\":{\"name\":\"2015 Symposium on VLSI Technology (VLSI Technology)\",\"volume\":\"540 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-06-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 Symposium on VLSI Technology (VLSI Technology)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2015.7223710\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Symposium on VLSI Technology (VLSI Technology)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2015.7223710","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Considerations for efficient contact resistivity reduction via Fermi Level depinning - impact of MIS contacts on 10nm node nMOSFET DC characteristics
In the overwhelming majority of cases, current-voltage characteristics of metal-based contacts on semiconductors are non-linear around 0V even for degenerate interfacial doping levels. Any contact resistivity specification is therefore meaningless without the knowledge of the effective bias across the contact. For the first time, the efficiency of a dielectric insertion for contact resistance reduction was properly evaluated by solving the self-consistent case of voltage sharing for an aggressively scaled transistor flanked by two trench Metal/ Insulator/Semiconductor (MIS) contacts. We found that leveraging the Fermi Level depinning via optimized MIS contacts could lead to a +92% drive current (VGS=Vdd=0.7V) increase versus a Titanium liner-based silicidation-free approach.