通过费米能级沉降有效降低接触电阻率的考虑——MIS触点对10nm节点nMOSFET直流特性的影响

J. Borrel, L. Hutin, O. Rozeau, P. Batude, T. Poiroux, F. Nemouchi, M. Vinet
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引用次数: 11

摘要

在绝大多数情况下,即使在简并界面掺杂水平下,半导体上金属基触点的电流-电压特性在0V左右也是非线性的。因此,如果不知道接触面上的有效偏置,任何接触电阻率规格都是没有意义的。第一次,通过解决由两个沟槽金属/绝缘体/半导体(MIS)触点两侧的积极缩放晶体管的电压共享自一致情况,适当地评估了介电插入降低触点电阻的效率。我们发现,与基于钛衬里的无硅化方法相比,通过优化的MIS触点利用费米能级脱屑可以导致+92%的驱动电流(VGS=Vdd=0.7V)增加。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Considerations for efficient contact resistivity reduction via Fermi Level depinning - impact of MIS contacts on 10nm node nMOSFET DC characteristics
In the overwhelming majority of cases, current-voltage characteristics of metal-based contacts on semiconductors are non-linear around 0V even for degenerate interfacial doping levels. Any contact resistivity specification is therefore meaningless without the knowledge of the effective bias across the contact. For the first time, the efficiency of a dielectric insertion for contact resistance reduction was properly evaluated by solving the self-consistent case of voltage sharing for an aggressively scaled transistor flanked by two trench Metal/ Insulator/Semiconductor (MIS) contacts. We found that leveraging the Fermi Level depinning via optimized MIS contacts could lead to a +92% drive current (VGS=Vdd=0.7V) increase versus a Titanium liner-based silicidation-free approach.
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