Y. Yamamoto, H. Makiyama, T. Yamashita, H. Oda, S. Kamohara, N. Sugii, Y. Yamaguchi, T. Mizutani, M. Kobayashi, T. Hiramoto
{"title":"Novel single p+poly-Si/Hf/SiON gate stack technology on silicon-on-thin-buried-oxide (SOTB) for ultra-low leakage applications","authors":"Y. Yamamoto, H. Makiyama, T. Yamashita, H. Oda, S. Kamohara, N. Sugii, Y. Yamaguchi, T. Mizutani, M. Kobayashi, T. Hiramoto","doi":"10.1109/VLSIT.2015.7223665","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223665","url":null,"abstract":"We demonstrate a cost effective 65-nm SOTB CMOS technology for ultra-low leakage applications. Novel single p+poly-Si/Hf/SiON gate stack of mid-gap work function and precise GIDL control achieved ultra-low leakage of 0.2 pA/μm, which corresponds to approx. 100nA/chip (100k gate logic). Now the SOTB technology can provide three options from ultra-low voltage to ultra-low leakage that covers a wide variety of applications in the Internet of Things (IoT) era.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126274962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Djara, V. Deshpande, E. Uccelli, N. Daix, D. Caimi, C. Rossel, M. Sousa, H. Siegwart, C. Marchiori, J. Hartmann, K. Shiu, C.-W. Weng, M. Krishnan, M. Lofaro, R. Steiner, D. Sadana, D. Lubyshev, A. Liu, L. Czornomaz, J. Fompeyrine
{"title":"An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch","authors":"V. Djara, V. Deshpande, E. Uccelli, N. Daix, D. Caimi, C. Rossel, M. Sousa, H. Siegwart, C. Marchiori, J. Hartmann, K. Shiu, C.-W. Weng, M. Krishnan, M. Lofaro, R. Steiner, D. Sadana, D. Lubyshev, A. Liu, L. Czornomaz, J. Fompeyrine","doi":"10.1109/VLSIT.2015.7223668","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223668","url":null,"abstract":"We report on the first demonstration of ultra-thin body (50 nm), low defectivity 200 mm InGaAs-on-insulator (-OI) fabricated by direct wafer bonding technique (DWB) as well as a replacement gate process for self-aligned fully depleted InGaAs MOSFETs. These combined achievements highlight the viability of our approach for the VLSI integration of InGaAs at advanced nodes. Short channel replacement gate (RMG) and Gate-first (GF) FETs are reported for the first time using InGaAs-OI wafers with a 120nm contact-to-contact pitch. Record ION (118 μA/μm) at fixed operating voltage of 0.5V for InGaAs devices on Si is achieved on 50-nm-Lg RMG FinFETs. Both schemes feature highly scaled fins (down to 15 nm). Compared to a GF integration flow, RMG devices exhibit better Ion and DIBL characteristics. We also demonstrate FETs with 70 nm contacts and 120 nm pitch achieving high-ION.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123207227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Senju Yamazaki, S. Tanakamaru, Sakuya Suzuki, T. Iwasaki, Shogo Hachiya, K. Takeuchi
{"title":"Reliability enhancement of 1Xnm TLC for cold flash and millennium memories","authors":"Senju Yamazaki, S. Tanakamaru, Sakuya Suzuki, T. Iwasaki, Shogo Hachiya, K. Takeuchi","doi":"10.1109/VLSIT.2015.7223642","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223642","url":null,"abstract":"Endurance and retention are measured in 1Xnm Triple Level Cell (TLC) NAND and the flexible nLC scheme (flex-nLC) is proposed to improve reliability. This method enables the use of lowest-cost TLC NAND as is, in long term storage applications such as cold flash and digital archive: millennium memory, which have 20 and 1000 years retention, respectively.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123733526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chen Zhou, Xiaofei Wang, R. Fung, S. Wen, R. Wong, C. Kim
{"title":"High frequency AC electromigration lifetime measurements from a 32nm test chip","authors":"Chen Zhou, Xiaofei Wang, R. Fung, S. Wen, R. Wong, C. Kim","doi":"10.1109/VLSIT.2015.7223696","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223696","url":null,"abstract":"A test circuit for studying Electromigration (EM) effects under realistic high frequency AC stress was implemented in a 32nm High-k Metal Gate (HKMG) process. Four different stress patterns (DC, pulsed DC, square AC and real AC) can be generated using on-chip circuits. Local heaters are used to raise the die temperature to >300°C for accelerated testing. Experiment results over 52.7 hours show no AC stress induced failures under 325°C, 1.5V (driver supply) at 200 MHz and 900 MHz. However, the pre-AC stress had an impact on the DC EM distribution.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124076119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lili Yu, D. El-Damak, S. Ha, S. Rakheja, X. Ling, J. Kong, D. Antoniadis, A. Chandrakasan, T. Palacios
{"title":"MoS2 FET fabrication and modeling for large-scale flexible electronics","authors":"Lili Yu, D. El-Damak, S. Ha, S. Rakheja, X. Ling, J. Kong, D. Antoniadis, A. Chandrakasan, T. Palacios","doi":"10.1109/VLSIT.2015.7223655","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223655","url":null,"abstract":"We present a state-of-the-art fabrication technology and physics-based model for molybdenum disulfide (MoS2) field effect transistors (FETs) to realize large-scale circuits. Uniform and large area chemical vapor deposition (CVD) growth of monolayer MoS2 was achieved by using perylene-3,4,9, 10-tetracarboxylic acid tetrapotassium salt (PTAS) seeding. Then, a gate first process results in enhancement mode FETs and also reduces performance variation and enables better process control. In addition, a Verilog-A compact model precisely predicts the performance of the fabricated MoS2 FETs and eases the large-scale integrated design. By using this technology, a switched capacitor DC-DC converter is implemented, and the measurement of the converter shows good agreement with the simulations.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124082101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Mertens, R. Ritzenthaler, H. Arimura, J. Franco, F. Sebaai, A. Hikavyy, B. Pawlak, V. Machkaoutsan, K. Devriendt, D. Tsvetanova, A. Milenin, L. Witters, A. Dangol, E. Vancoille, H. Bender, M. Badaroglu, F. Holsteyns, K. Barla, D. Mocuta, N. Horiguchi, A. Thean
{"title":"Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal","authors":"H. Mertens, R. Ritzenthaler, H. Arimura, J. Franco, F. Sebaai, A. Hikavyy, B. Pawlak, V. Machkaoutsan, K. Devriendt, D. Tsvetanova, A. Milenin, L. Witters, A. Dangol, E. Vancoille, H. Bender, M. Badaroglu, F. Holsteyns, K. Barla, D. Mocuta, N. Horiguchi, A. Thean","doi":"10.1109/VLSIT.2015.7223654","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223654","url":null,"abstract":"We demonstrate Si-cap-free SiGe p-channel FinFETs and gate-all-around (GAA) FETs in a replacement metal gate (RMG) process, for Ge contents of 25% and 45%. We show that the performance of these devices is substantially improved by high-pressure (HP) deuterium (D2) anneal, which is ascribed to a 2x reduction in interface trap density (DIT). Furthermore, it is found that (1) TMAH treatment of SiGe prior to HK deposition and (2) HK post-deposition annealing (PDA) are beneficial for DIT reduction as well, and that NBTI reliability is improved by both HP D2 anneal and TMAH treatment.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122909210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Device design guideline for steep slope ferroelectric FET using negative capacitance in sub-0.2V operation: Operation speed, material requirement and energy efficiency","authors":"M. Kobayashi, T. Hiramoto","doi":"10.1109/VLSIT.2015.7223678","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223678","url":null,"abstract":"We have shown a practical device design guideline for sub-0.2V ultra-low power, steep slope ferroelectric FET using negative capacitance (NC) focusing on operation speed, material requirement, and energy efficiency for the first time. The operation speed is determined by finite switching time of ferroelectric polarization. For low supply voltage and hysteresis-free design, there exists a ferroelectric material parameter window to maximize the benefit of steep slope by NC. By the optimized device design, the energy efficiency is improved by 2.5x. The minimum energy voltage is pushed down to sub-0.2V range.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127954708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Honjo, H. Sato, S. Ikeda, S. Sato, T. Watanebe, S. Miura, T. Nasuno, Y. Noguchi, M. Yasuhira, T. Tanigawa, H. Koike, M. Muraguchi, M. Niwa, K. Ito, H. Ohno, T. Endoh
{"title":"10 nmf perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction with over 400°C high thermal tolerance by boron diffusion control","authors":"H. Honjo, H. Sato, S. Ikeda, S. Sato, T. Watanebe, S. Miura, T. Nasuno, Y. Noguchi, M. Yasuhira, T. Tanigawa, H. Koike, M. Muraguchi, M. Niwa, K. Ito, H. Ohno, T. Endoh","doi":"10.1109/VLSIT.2015.7223661","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223661","url":null,"abstract":"We have developed a perpendicular-anisotropy magnetic tunnel junction (p-MTJ) stack with CoFeB free layer and Co/Pt multilayer based synthetic ferrimagnetic (SyF) pinned layer that withstand annealing at a temperature up to 420°C (that compatible with CMOS BEOL process) by controlling boron diffusion. We demonstrated the 10 nmφ p-MTJ with double CoFeB/MgO interface tolerable against 400°C annealing which is a requisite building block for realization of high density spin transfer torque magnetic random access memory (STT-MRAM) in reduced dimensions.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121024770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Batude, C. Fenouillet-Béranger, L. Pasini, V. Lu, F. Deprat, L. Brunet, B. Sklénard, F. Piegas-Luce, M. Cassé, B. Mathieu, O. Billoint, G. Cibrario, O. Turkyilmaz, H. Sarhan, S. Thuries, L. Hutin, S. Sollier, J. Widiez, L. Hortemel, C. Tabone, M.-P. Samson, B. Previtali, N. Rambal, F. Ponthenier, J. Mazurier, R. Beneyton, M. Bidaud, E. Josse, E. Petitprez, O. Rozeau, M. Rivoire, C. Euvard-Colnat, A. Seignard, F. Fournel, L. Benaissa, P. Coudrain, P. Leduc, J. Hartmann, P. Besson, S. Kerdilès, C. Bout, F. Nemouchi, A. Royer, C. Agraffeil, Gérard Ghibaudo, T. Signamarcheix, Michel Haond, F. Clermidy, O. Faynot, M. Vinet
{"title":"3DVLSI with CoolCube process: An alternative path to scaling","authors":"P. Batude, C. Fenouillet-Béranger, L. Pasini, V. Lu, F. Deprat, L. Brunet, B. Sklénard, F. Piegas-Luce, M. Cassé, B. Mathieu, O. Billoint, G. Cibrario, O. Turkyilmaz, H. Sarhan, S. Thuries, L. Hutin, S. Sollier, J. Widiez, L. Hortemel, C. Tabone, M.-P. Samson, B. Previtali, N. Rambal, F. Ponthenier, J. Mazurier, R. Beneyton, M. Bidaud, E. Josse, E. Petitprez, O. Rozeau, M. Rivoire, C. Euvard-Colnat, A. Seignard, F. Fournel, L. Benaissa, P. Coudrain, P. Leduc, J. Hartmann, P. Besson, S. Kerdilès, C. Bout, F. Nemouchi, A. Royer, C. Agraffeil, Gérard Ghibaudo, T. Signamarcheix, Michel Haond, F. Clermidy, O. Faynot, M. Vinet","doi":"10.1109/VLSIT.2015.7223698","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223698","url":null,"abstract":"3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm2. This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115861736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Pyzyna, R. Bruce, M. Lofaro, H. Tsai, C. Witt, L. Gignac, M. Brink, M. Guillorn, G. Fritz, H. Miyazoe, D. Klaus, E. Joseph, K. Rodbell, C. Lavoie, D. Park
{"title":"Resistivity of copper interconnects beyond the 7 nm node","authors":"A. Pyzyna, R. Bruce, M. Lofaro, H. Tsai, C. Witt, L. Gignac, M. Brink, M. Guillorn, G. Fritz, H. Miyazoe, D. Klaus, E. Joseph, K. Rodbell, C. Lavoie, D. Park","doi":"10.1109/VLSIT.2015.7223712","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223712","url":null,"abstract":"The resistivity of damascene copper is measured at pitch ranging down to 40 nm and copper cross-sectional area as low as 140 nm2. Metallization by copper reflow is demonstrated at 28 nm pitch with patterning by directed self-assembly (DSA). Extremely low line-edge-roughness (LER) is attained by surface reconstruction of a single crystal silicon mask. Variation of LER is found to have no impact on resistivity. A resistivity benefit is found for wires with nearly bamboo grain structure, offering the promise of improved performance beyond the 7 nm node if grain size can be controlled.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128142524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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