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2015 Symposium on VLSI Technology (VLSI Technology)最新文献

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2.8-GB/s-write and 670-MB/s-erase operations of a 3D vertical chain-cell-type phase-change-memory array 三维垂直链单元型相变存储器阵列的2.8 gb /s写入和670 mb /s擦除操作
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223705
K. Kurotsuchi, Y. Sasago, H. Yoshitake, H. Minemura, Y. Anzai, Y. Fujisaki, T. Takahama, T. Takahashi, T. Mine, A. Shima, K. Fujisaki, T. Kobayashi
{"title":"2.8-GB/s-write and 670-MB/s-erase operations of a 3D vertical chain-cell-type phase-change-memory array","authors":"K. Kurotsuchi, Y. Sasago, H. Yoshitake, H. Minemura, Y. Anzai, Y. Fujisaki, T. Takahama, T. Takahashi, T. Mine, A. Shima, K. Fujisaki, T. Kobayashi","doi":"10.1109/VLSIT.2015.7223705","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223705","url":null,"abstract":"A high-programming-throughput three-dimensional (3D) vertical chain-cell-type phase-change memory (VCCPCM) array for a next-generation storage device was fabricated. To increase the number of write cells at one time by reducing resistance of bit and source lines, the VCCPCM array includes plate electrodes and double-gate vertical-chain-selection MOSs with 5-nm-thick poly-Si channels. In addition, CO2 laser annealing enhances the drivability of a poly-Si cell MOS to 680 μA/μm to suppress energy loss in the cell MOS. In addition to write throughput, erase throughput is increased by erasing memory cells in a “bundle” by channel heating (called “bundle erase”). GeSbTe CVD with high uniformity is also developed.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"286 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132638530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
High performance, integrated 1T1R oxide-based oscillator: Stack engineering for low-power operation in neural network applications 高性能，集成的1T1R氧化物振荡器:用于神经网络应用中低功耗操作的堆栈工程
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223672
A. A. Sharma, T. C. Jackson, M. Schulaker, C. Kuo, C. Augustine, J. Bain, H. Wong, S. Mitra, L. Pileggi, J. Weldon
{"title":"High performance, integrated 1T1R oxide-based oscillator: Stack engineering for low-power operation in neural network applications","authors":"A. A. Sharma, T. C. Jackson, M. Schulaker, C. Kuo, C. Augustine, J. Bain, H. Wong, S. Mitra, L. Pileggi, J. Weldon","doi":"10.1109/VLSIT.2015.7223672","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223672","url":null,"abstract":"Brain-inspired non-Boolean computing paradigms are gaining wide interest due to their error resilient nature and massive parallelism. This work explores oxide-based compact oscillators for oscillatory neural networks (ONN). We demonstrate for the first time, best in class high-frequency performance at 500 MHz and low power (<; 200 μW). The superior figures of merit are achieved due to device engineering to give maximum swing at low power and integration as a 1T1R structure. We show frequency control over 2 orders of magnitude by varying the gate voltage and show its applicability to an ONN-based associative memory.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129354790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
High performance low temperature activated devices and optimization guidelines for 3D VLSI integration of FD, TriGate, FinFET on insulator 在绝缘体上集成FD, TriGate, FinFET的3D VLSI的高性能低温激活器件和优化指南
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223699
L. Pasini, P. Batude, M. Cassé, B. Mathieu, B. Sklénard, F. P. Luce, S. Reboh, N. Bernier, C. Tabone, O. Rozeau, S. Martini, C. Fenouillet-Béranger, L. Brunet, G. Audoit, D. Lafond, F. Aussenac, F. Allain, G. Romano, S. Barraud, N. Rambal, V. Barral, L. Hutin, J. Hartmann, P. Besson, S. Kerdilès, M. Haond, G. Ghibaudo, M. Vinet
{"title":"High performance low temperature activated devices and optimization guidelines for 3D VLSI integration of FD, TriGate, FinFET on insulator","authors":"L. Pasini, P. Batude, M. Cassé, B. Mathieu, B. Sklénard, F. P. Luce, S. Reboh, N. Bernier, C. Tabone, O. Rozeau, S. Martini, C. Fenouillet-Béranger, L. Brunet, G. Audoit, D. Lafond, F. Aussenac, F. Allain, G. Romano, S. Barraud, N. Rambal, V. Barral, L. Hutin, J. Hartmann, P. Besson, S. Kerdilès, M. Haond, G. Ghibaudo, M. Vinet","doi":"10.1109/VLSIT.2015.7223699","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223699","url":null,"abstract":"3D VLSI integration is a promising alternative path towards CMOS scalability. It requires Low Temperature (LT) processing (≤600°C) for top FET fabrication. In this work, record performance is demonstrated for LT TriGate and FDSOI devices using Solid Phase Epitaxy (SPE). Optimization guidelines for further performance improvement are given for FD, TriGate and FinFET on insulator with the constraint of 14nm node channel strain preservation. This work concludes that extension first process scheme (implantation before the raised source and drain epitaxy) is required for FDSOI and TriGate architectures.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130766603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Cu diffusion barrier: Graphene benchmarked to TaN for ultimate interconnect scaling Cu扩散屏障:石墨烯以TaN为基准，用于最终互连缩放
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223713
Ling Li, Xiangyu Chen, Ching-Hua Wang, Seunghyun Lee, Ji Cao, S. Roy, M. Arnold, H. Wong
{"title":"Cu diffusion barrier: Graphene benchmarked to TaN for ultimate interconnect scaling","authors":"Ling Li, Xiangyu Chen, Ching-Hua Wang, Seunghyun Lee, Ji Cao, S. Roy, M. Arnold, H. Wong","doi":"10.1109/VLSIT.2015.7223713","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223713","url":null,"abstract":"The advantages of graphene diffusion barrier are studied and benchmarked to the industry-standard barrier material TaN for the first time. Even when the wire width is scaled to 10 nm, the effective resistivity of the Cu interconnect is maintained near the intrinsic value of Cu using a 3 Å single layer graphene (SLG) barrier. In the time dependent dielectric breakdown (TDDB) test, 4 nm multi-layer graphene (MLG) gives 6.5X shorter mean time to fail (MTTF) than 4 nm TaN. However, when the barrier thickness is reduced, 3 Å single-layer graphene (SLG) gives 3.3X longer MTTF than 2 nm TaN, showing that SLG has better scaling potential. The influences of SLG grain size and various transfer methods are presented for further improving the SLG barrier performance.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133734278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Greater than 2-bits/cell MLC storage for ultra high density phase change memory using a novel sensing scheme 使用一种新颖的传感方案，用于超高密度相变存储器的大于2位/单元的MLC存储
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223706
J. Y. Wu, W. Khwa, M. Lee, H. Li, S. Lai, T. Su, M. Wei, T. Wang, M. BrightSky, T. S. Chen, W. Chien, S. Kim, R. Cheek, H. Cheng, E. Lai, Y. Zhu, H. Lung, C. Lam
{"title":"Greater than 2-bits/cell MLC storage for ultra high density phase change memory using a novel sensing scheme","authors":"J. Y. Wu, W. Khwa, M. Lee, H. Li, S. Lai, T. Su, M. Wei, T. Wang, M. BrightSky, T. S. Chen, W. Chien, S. Kim, R. Cheek, H. Cheng, E. Lai, Y. Zhu, H. Lung, C. Lam","doi":"10.1109/VLSIT.2015.7223706","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223706","url":null,"abstract":"Multi-level-cell (MLC) is a critical technology to achieve low bit cost for phase change memory. However, resistance drift is an intrinsic material property that kills memory window and imposes formidable challenges for MLC. In this work, we report a radically different sensing concept that exploits the non-linear R-V characteristics of PCM that can easily accommodate 8 resistance levels in three independent 10X sensing windows (100KΩ~1MΩ × 3) all on same read speed. Each sensing window only needs to store 2~3 resistance levels instead of 8 levels needed in conventional MLC method, thus can tolerate resistance drift without closing the memory windows. A maximum of 16 levels of MLC is demonstrated on a 256Mb chip that is suitable for 4-bits/cell application.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116325508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
New industry standard FinFET compact model for future technology nodes 面向未来技术节点的新型行业标准FinFET紧凑模型
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223704
S. Khandelwal, J. Duarte, A. Medury, Y. Chauhan, C. Hu
{"title":"New industry standard FinFET compact model for future technology nodes","authors":"S. Khandelwal, J. Duarte, A. Medury, Y. Chauhan, C. Hu","doi":"10.1109/VLSIT.2015.7223704","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223704","url":null,"abstract":"A new production ready compact model for future FinFETs is presented. This single unified model can model FinFETs with realistic fin shapes including rectangle, triangle, circle and any shape in between. New mobility models support Ge p-FinFETs and InGaAs n-FinFETs. A new quantum effects model enables accurate modeling of III-V FinFETs. Special attention is paid to shape agnostic short-channel effect model for aggressive Lg scaling and body bias model for FinFETs on bulk substrates. With its accuracy verified with experimental data and TCAD, this computationally efficient model is an ideal turn-key solution for simulation and design of future heterogeneous circuits.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125202109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Quantitative endurance failure model for filamentary RRAM 细丝RRAM的定量耐久性失效模型
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223673
Robin Degraeve, A. Fantini, P. Roussel, L. Goux, A. Costantino, C. Y. Chen, S. Clima, B. Govoreanu, D. Linten, Aaron Thean, Malgorzata Jurczak
{"title":"Quantitative endurance failure model for filamentary RRAM","authors":"Robin Degraeve, A. Fantini, P. Roussel, L. Goux, A. Costantino, C. Y. Chen, S. Clima, B. Govoreanu, D. Linten, Aaron Thean, Malgorzata Jurczak","doi":"10.1109/VLSIT.2015.7223673","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223673","url":null,"abstract":"Endurance in filamentary RRAM is modeled in the framework of the hourglass model. Two failure modes are distinguished: (i) stochastic set failure is caused by defect generation near the bottom electrode, and (ii) resistive window changes are controlled by T-activated changes of the number of filament vacancies. Bottom electrode/oxide interface optimization is the prime knob for endurance improvement. This model enables quantitative and predictive endurance simulations.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128822005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
III–V and Ge/strained SOI tunneling FET technologies for low power LSIs 用于低功耗lsi的III-V和Ge/应变SOI隧道效应场效应管技术
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223687
S. Takagi, M. Kim, M. Noguchi, S. Ji, K. Nishi, M. Takenaka
{"title":"III–V and Ge/strained SOI tunneling FET technologies for low power LSIs","authors":"S. Takagi, M. Kim, M. Noguchi, S. Ji, K. Nishi, M. Takenaka","doi":"10.1109/VLSIT.2015.7223687","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223687","url":null,"abstract":"We have demonstrated high performance operation of planar-type tunnel field-effect transistors (TFETs) using Ge/ III-V materials. Tensile strain in Si channels combined with the Ge source can enhance the tunneling current because of the reduced effective bandgap. The fabricated Ge/sSOI (1.1 %) TFETs show high I<sub>on</sub>/I<sub>off</sub> ratio over 10<sup>7</sup> and steep minimum subthreshold slope (SS) of 28 mV/dec. It is found that I<sub>on</sub> and SS are improved by positive back bias. We have also demonstrated the operation of high I<sub>on</sub>/I<sub>off</sub> and low SS planar-type InGaAs Tunnel FETs with Zn-diffused source junctions. Solid-phase Zn diffusion can realize steep-profile and defect-less p<sup>+</sup>/n source junctions. The small S.S. of 64 mV/dec and large I<sub>on</sub>/I<sub>off</sub> ratio over 10<sup>6</sup> have been realized in the planar-type III-V TFETs.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114356919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Energy efficient 1-transistor active pixel sensor (APS) with FD SOI tunnel FET 具有FD SOI隧道场效应管的高能效1晶体管有源像素传感器(APS)
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223681
N. Dagtekin, A. Ionescu
{"title":"Energy efficient 1-transistor active pixel sensor (APS) with FD SOI tunnel FET","authors":"N. Dagtekin, A. Ionescu","doi":"10.1109/VLSIT.2015.7223681","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223681","url":null,"abstract":"This paper presents the first energy efficient highly compact concept of active pixel sensor built with a single partially-gated tunnel FET (TFET). Experimental results show that the transistor characteristics of the investigated TFETs are nonlinearly modulated by optical excitation and a transistor gain that is a function of irradiance and bias conditions is reported for the first time. A memory effect is observed and exploited when the backgate is used as a secondary gate to control charge storing mechanism in the body, similarly to backside illuminated pixels. Compared to CMOS, 1T-TFET pixel offers high sensitivity (detection limit <; 2pW/μm2 in visible light), low power operation, improved temperature stability (validation at 70°C) and high compactness (1T architecture with pixel size of ~10×1μm2 in this work).","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134536592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
AC NBTI of Ge pMOSFETs: Impact of energy alternating defects on lifetime prediction Ge pmosfet的交流NBTI:能量交替缺陷对寿命预测的影响
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223692
J. Ma, W. Zhang, J. F. Zhang, Z. Ji, B. Benbakhti, J. Franco, J. Mitard, L. Witters, N. Collaert, G. Groeseneken
{"title":"AC NBTI of Ge pMOSFETs: Impact of energy alternating defects on lifetime prediction","authors":"J. Ma, W. Zhang, J. F. Zhang, Z. Ji, B. Benbakhti, J. Franco, J. Mitard, L. Witters, N. Collaert, G. Groeseneken","doi":"10.1109/VLSIT.2015.7223692","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223692","url":null,"abstract":"For the first time, AC lifetime in Si-cap/Ge and GeO2/Ge pMOSFETs is investigated and it must not be predicted by the conventional DC stress method with a measurement delay. This is because the energy alternating defects are generated in Ge devices but not in Si, which introduces additional generation under DC stress.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132710289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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