S. Takagi, M. Kim, M. Noguchi, S. Ji, K. Nishi, M. Takenaka
{"title":"用于低功耗lsi的III-V和Ge/应变SOI隧道效应场效应管技术","authors":"S. Takagi, M. Kim, M. Noguchi, S. Ji, K. Nishi, M. Takenaka","doi":"10.1109/VLSIT.2015.7223687","DOIUrl":null,"url":null,"abstract":"We have demonstrated high performance operation of planar-type tunnel field-effect transistors (TFETs) using Ge/ III-V materials. Tensile strain in Si channels combined with the Ge source can enhance the tunneling current because of the reduced effective bandgap. The fabricated Ge/sSOI (1.1 %) TFETs show high I<sub>on</sub>/I<sub>off</sub> ratio over 10<sup>7</sup> and steep minimum subthreshold slope (SS) of 28 mV/dec. It is found that I<sub>on</sub> and SS are improved by positive back bias. We have also demonstrated the operation of high I<sub>on</sub>/I<sub>off</sub> and low SS planar-type InGaAs Tunnel FETs with Zn-diffused source junctions. Solid-phase Zn diffusion can realize steep-profile and defect-less p<sup>+</sup>/n source junctions. The small S.S. of 64 mV/dec and large I<sub>on</sub>/I<sub>off</sub> ratio over 10<sup>6</sup> have been realized in the planar-type III-V TFETs.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":"{\"title\":\"III–V and Ge/strained SOI tunneling FET technologies for low power LSIs\",\"authors\":\"S. Takagi, M. Kim, M. Noguchi, S. Ji, K. Nishi, M. Takenaka\",\"doi\":\"10.1109/VLSIT.2015.7223687\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have demonstrated high performance operation of planar-type tunnel field-effect transistors (TFETs) using Ge/ III-V materials. Tensile strain in Si channels combined with the Ge source can enhance the tunneling current because of the reduced effective bandgap. The fabricated Ge/sSOI (1.1 %) TFETs show high I<sub>on</sub>/I<sub>off</sub> ratio over 10<sup>7</sup> and steep minimum subthreshold slope (SS) of 28 mV/dec. It is found that I<sub>on</sub> and SS are improved by positive back bias. We have also demonstrated the operation of high I<sub>on</sub>/I<sub>off</sub> and low SS planar-type InGaAs Tunnel FETs with Zn-diffused source junctions. Solid-phase Zn diffusion can realize steep-profile and defect-less p<sup>+</sup>/n source junctions. The small S.S. of 64 mV/dec and large I<sub>on</sub>/I<sub>off</sub> ratio over 10<sup>6</sup> have been realized in the planar-type III-V TFETs.\",\"PeriodicalId\":181654,\"journal\":{\"name\":\"2015 Symposium on VLSI Technology (VLSI Technology)\",\"volume\":\"53 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-06-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"23\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 Symposium on VLSI Technology (VLSI Technology)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2015.7223687\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Symposium on VLSI Technology (VLSI Technology)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2015.7223687","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
III–V and Ge/strained SOI tunneling FET technologies for low power LSIs
We have demonstrated high performance operation of planar-type tunnel field-effect transistors (TFETs) using Ge/ III-V materials. Tensile strain in Si channels combined with the Ge source can enhance the tunneling current because of the reduced effective bandgap. The fabricated Ge/sSOI (1.1 %) TFETs show high Ion/Ioff ratio over 107 and steep minimum subthreshold slope (SS) of 28 mV/dec. It is found that Ion and SS are improved by positive back bias. We have also demonstrated the operation of high Ion/Ioff and low SS planar-type InGaAs Tunnel FETs with Zn-diffused source junctions. Solid-phase Zn diffusion can realize steep-profile and defect-less p+/n source junctions. The small S.S. of 64 mV/dec and large Ion/Ioff ratio over 106 have been realized in the planar-type III-V TFETs.