三维垂直链单元型相变存储器阵列的2.8 gb /s写入和670 mb /s擦除操作

2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI:10.1109/VLSIT.2015.7223705

K. Kurotsuchi, Y. Sasago, H. Yoshitake, H. Minemura, Y. Anzai, Y. Fujisaki, T. Takahama, T. Takahashi, T. Mine, A. Shima, K. Fujisaki, T. Kobayashi

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引用次数: 10

摘要

制备了用于下一代存储器件的高编程吞吐量三维垂直链单元相变存储器(VCCPCM)阵列。为了通过减少位线和源线的电阻来增加一次写入单元的数量，VCCPCM阵列包括板电极和具有5纳米厚多晶硅通道的双栅垂直链选择MOSs。此外，CO2激光退火将多晶硅电池MOS的可驱动性提高到680 μA/μm，抑制了电池MOS的能量损失。除了写入吞吐量之外，擦除吞吐量还可以通过通道加热擦除“束”中的内存单元(称为“束擦除”)来提高。研制出了均匀性高的gesbcvd。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2.8-GB/s-write and 670-MB/s-erase operations of a 3D vertical chain-cell-type phase-change-memory array

A high-programming-throughput three-dimensional (3D) vertical chain-cell-type phase-change memory (VCCPCM) array for a next-generation storage device was fabricated. To increase the number of write cells at one time by reducing resistance of bit and source lines, the VCCPCM array includes plate electrodes and double-gate vertical-chain-selection MOSs with 5-nm-thick poly-Si channels. In addition, CO2 laser annealing enhances the drivability of a poly-Si cell MOS to 680 μA/μm to suppress energy loss in the cell MOS. In addition to write throughput, erase throughput is increased by erasing memory cells in a “bundle” by channel heating (called “bundle erase”). GeSbTe CVD with high uniformity is also developed.

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2015 Symposium on VLSI Technology (VLSI Technology)

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