替换金属栅极工艺中的无硅帽SiGe p沟道finfet和栅极全能晶体管:高压氘退火降低界面陷阱密度和提高性能

2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI:10.1109/VLSIT.2015.7223654

H. Mertens, R. Ritzenthaler, H. Arimura, J. Franco, F. Sebaai, A. Hikavyy, B. Pawlak, V. Machkaoutsan, K. Devriendt, D. Tsvetanova, A. Milenin, L. Witters, A. Dangol, E. Vancoille, H. Bender, M. Badaroglu, F. Holsteyns, K. Barla, D. Mocuta, N. Horiguchi, A. Thean

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引用次数: 46

摘要

我们展示了在替代金属栅极(RMG)工艺中无硅帽SiGe p沟道finfet和栅极全能(GAA) fet, Ge含量分别为25%和45%。我们发现，高压(HP)氘(D2)退火大大改善了这些器件的性能，这归因于界面陷阱密度(DIT)降低了2倍。此外，发现(1)在HK沉积前对SiGe进行TMAH处理和(2)HK沉积后退火(PDA)也有利于降低DIT，并且hpd2退火和TMAH处理都提高了NBTI的可靠性。

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Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

We demonstrate Si-cap-free SiGe p-channel FinFETs and gate-all-around (GAA) FETs in a replacement metal gate (RMG) process, for Ge contents of 25% and 45%. We show that the performance of these devices is substantially improved by high-pressure (HP) deuterium (D2) anneal, which is ascribed to a 2x reduction in interface trap density (DIT). Furthermore, it is found that (1) TMAH treatment of SiGe prior to HK deposition and (2) HK post-deposition annealing (PDA) are beneficial for DIT reduction as well, and that NBTI reliability is improved by both HP D2 anneal and TMAH treatment.

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2015 Symposium on VLSI Technology (VLSI Technology)

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