Resistivity of copper interconnects beyond the 7 nm node

A. Pyzyna, R. Bruce, M. Lofaro, H. Tsai, C. Witt, L. Gignac, M. Brink, M. Guillorn, G. Fritz, H. Miyazoe, D. Klaus, E. Joseph, K. Rodbell, C. Lavoie, D. Park
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引用次数: 20

Abstract

The resistivity of damascene copper is measured at pitch ranging down to 40 nm and copper cross-sectional area as low as 140 nm2. Metallization by copper reflow is demonstrated at 28 nm pitch with patterning by directed self-assembly (DSA). Extremely low line-edge-roughness (LER) is attained by surface reconstruction of a single crystal silicon mask. Variation of LER is found to have no impact on resistivity. A resistivity benefit is found for wires with nearly bamboo grain structure, offering the promise of improved performance beyond the 7 nm node if grain size can be controlled.
7nm节点以上铜互连的电阻率
damascene铜的电阻率在间距范围低至40 nm,铜横截面积低至140 nm2时测量。采用定向自组装(DSA)技术,在28nm的间距上进行了铜回流金属化。通过对单晶硅掩膜进行表面重建,获得了极低的线边粗糙度(LER)。LER的变化对电阻率没有影响。研究发现,接近竹晶结构的导线具有电阻率优势,如果晶粒尺寸可以控制,则有望提高7nm节点以上的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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