5nm及以上的垂直器件架构:器件和电路的影响

2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI:10.1109/VLSIT.2015.7223689

A. Thean, D. Yakimets, T. Huynh Bao, P. Schuddinck, S. Sakhare, M. Bardon, A. Sibaja-Hernandez, I. Ciofi, G. Eneman, A. Veloso, J. Ryckaert, P. Raghavan, A. Mercha, A. Mocuta, Z. Tokei, D. Verkest, P. Wambacq, K. De Meyer, N. Collaert

{"title":"5nm及以上的垂直器件架构:器件和电路的影响","authors":"A. Thean, D. Yakimets, T. Huynh Bao, P. Schuddinck, S. Sakhare, M. Bardon, A. Sibaja-Hernandez, I. Ciofi, G. Eneman, A. Veloso, J. Ryckaert, P. Raghavan, A. Mercha, A. Mocuta, Z. Tokei, D. Verkest, P. Wambacq, K. De Meyer, N. Collaert","doi":"10.1109/VLSIT.2015.7223689","DOIUrl":null,"url":null,"abstract":"Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"40","resultStr":"{\"title\":\"Vertical device architecture for 5nm and beyond: Device & circuit implications\",\"authors\":\"A. Thean, D. Yakimets, T. Huynh Bao, P. Schuddinck, S. Sakhare, M. Bardon, A. Sibaja-Hernandez, I. Ciofi, G. Eneman, A. Veloso, J. Ryckaert, P. Raghavan, A. Mercha, A. Mocuta, Z. Tokei, D. Verkest, P. Wambacq, K. De Meyer, N. Collaert\",\"doi\":\"10.1109/VLSIT.2015.7223689\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.\",\"PeriodicalId\":181654,\"journal\":{\"name\":\"2015 Symposium on VLSI Technology (VLSI Technology)\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-06-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"40\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 Symposium on VLSI Technology (VLSI Technology)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2015.7223689\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Symposium on VLSI Technology (VLSI Technology)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2015.7223689","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 40

摘要

垂直纳米线逻辑电路可以使器件密度扩展远远超出受栅极和触点放置限制的横向CMOS布局。在本文中，我们比较了垂直(vfet)栅极全能(GAA)晶体管与横向(lfet)瞄准5nm之间的性能，布局效率，SRAM设计和寄生。我们回顾了VFET器件和电路影响的一些独特考虑因素。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Vertical device architecture for 5nm and beyond: Device & circuit implications

Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2015 Symposium on VLSI Technology (VLSI Technology)

自引率

0.00%

发文量