A. Veloso, G. Hellings, M. Cho, E. Simoen, K. Devriendt, V. Paraschiv, E. Vecchio, Z. Tao, J. Versluijs, L. Souriau, H. Dekkers, S. Brus, J. Geypen, P. Lagrain, H. Bender, G. Eneman, P. Matagne, A. De Keersgieter, W. Fang, N. Collaert, A. Thean
{"title":"栅极全能nwfet与三栅极finfet:用于多vt CMOS的可控EWF调制的无结、无扩展和传统结器件","authors":"A. Veloso, G. Hellings, M. Cho, E. Simoen, K. Devriendt, V. Paraschiv, E. Vecchio, Z. Tao, J. Versluijs, L. Souriau, H. Dekkers, S. Brus, J. Geypen, P. Lagrain, H. Bender, G. Eneman, P. Matagne, A. De Keersgieter, W. Fang, N. Collaert, A. Thean","doi":"10.1109/VLSIT.2015.7223652","DOIUrl":null,"url":null,"abstract":"We report a comprehensive evaluation of different device architectures from a device and circuit performance viewpoint: gate-all-around (GAA) nanowire (NW) FETs vs. triple-gate finFETs, both built using various doping schemes. GAA devices are obtained via a fins release process, high density compatible, at replacement metal gate (RMG) module, and outperform others per footprint. Junctionless (JL) GAA-NWFETs with excellent electrostatics and smaller IOFF values yield ring oscillators (RO) with substantially lower power dissipation and considerably longer BTI lifetime. Improved reliability is also obtained for extensionless vs. reference FETs with conventional junctions, at comparable device and circuit performance. In addition, a TiAl-based EWF-metal is introduced for the first time in a GAA configuration resulting in higher performing, low-VT, n-type GAA-NWFETs and single-MG 6T-SRAM cells. Noise results show no significant impact of device architecture on gate stack integrity and some benefit for JL and TiAl-based GAA-NWFETs.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"273 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"44","resultStr":"{\"title\":\"Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS\",\"authors\":\"A. Veloso, G. Hellings, M. Cho, E. Simoen, K. Devriendt, V. Paraschiv, E. Vecchio, Z. Tao, J. Versluijs, L. Souriau, H. Dekkers, S. Brus, J. Geypen, P. Lagrain, H. Bender, G. Eneman, P. Matagne, A. De Keersgieter, W. Fang, N. Collaert, A. Thean\",\"doi\":\"10.1109/VLSIT.2015.7223652\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report a comprehensive evaluation of different device architectures from a device and circuit performance viewpoint: gate-all-around (GAA) nanowire (NW) FETs vs. triple-gate finFETs, both built using various doping schemes. GAA devices are obtained via a fins release process, high density compatible, at replacement metal gate (RMG) module, and outperform others per footprint. Junctionless (JL) GAA-NWFETs with excellent electrostatics and smaller IOFF values yield ring oscillators (RO) with substantially lower power dissipation and considerably longer BTI lifetime. Improved reliability is also obtained for extensionless vs. reference FETs with conventional junctions, at comparable device and circuit performance. In addition, a TiAl-based EWF-metal is introduced for the first time in a GAA configuration resulting in higher performing, low-VT, n-type GAA-NWFETs and single-MG 6T-SRAM cells. Noise results show no significant impact of device architecture on gate stack integrity and some benefit for JL and TiAl-based GAA-NWFETs.\",\"PeriodicalId\":181654,\"journal\":{\"name\":\"2015 Symposium on VLSI Technology (VLSI Technology)\",\"volume\":\"273 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-06-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"44\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 Symposium on VLSI Technology (VLSI Technology)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2015.7223652\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Symposium on VLSI Technology (VLSI Technology)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2015.7223652","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS
We report a comprehensive evaluation of different device architectures from a device and circuit performance viewpoint: gate-all-around (GAA) nanowire (NW) FETs vs. triple-gate finFETs, both built using various doping schemes. GAA devices are obtained via a fins release process, high density compatible, at replacement metal gate (RMG) module, and outperform others per footprint. Junctionless (JL) GAA-NWFETs with excellent electrostatics and smaller IOFF values yield ring oscillators (RO) with substantially lower power dissipation and considerably longer BTI lifetime. Improved reliability is also obtained for extensionless vs. reference FETs with conventional junctions, at comparable device and circuit performance. In addition, a TiAl-based EWF-metal is introduced for the first time in a GAA configuration resulting in higher performing, low-VT, n-type GAA-NWFETs and single-MG 6T-SRAM cells. Noise results show no significant impact of device architecture on gate stack integrity and some benefit for JL and TiAl-based GAA-NWFETs.