A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs

2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI:10.1109/VLSIT.2015.7223659

T. Yamashita, S. Mehta, V. Basker, R. Southwick, A. Kumar, R. Kambhampati, R. Sathiyanarayanan, J. Johnson, T. Hook, S. Cohen, J. Li, A. Madan, Z. Zhu, L. Tai, Y. Yao, P. Chinthamanipeta, M. Hopstaken, Z. Liu, D. Lu, F. Chen, S. Khan, D. Canaperi, B. Haran, J. Stathis, P. Oldiges, C. Lin, S. Narasimha, A. Bryant, W. Henson, S. Kanakasabapathy, K. Murali, T. Gow, D. Mcherron, H. Bu, M. Khare

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引用次数: 13

Abstract

FinFET has become the mainstream logic device architecture in recent technology nodes due to its superior electrostatic and leakage control [1,2,3,4]. However, parasitic capacitance has been a key performance detractor in 3D FinFETs. In this work, a novel low temperature ALD-based SiBCN material has been identified, with an optimized spacer RIE process developed to preserve the low-k value and provide compatibility with the down-stream processes. The material has been integrated into a manufacturable 14nm replacement-metal-gate (RMG) FinFET baseline with a demonstrated ~8% performance improvement in the RO delay with reliability meeting the technology requirement [4]. A guideline for spacer design consideration for 10nm node and beyond is also provided based on the comprehensive material properties and reliability evaluations.

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一种用于降低finfet寄生电容的新型ALD SiBCN低k间隔器

FinFET由于其优异的静电和泄漏控制能力，已成为近年技术节点中主流的逻辑器件架构[1,2,3,4]。然而，寄生电容一直是影响3D finfet性能的关键因素。在这项工作中，确定了一种新型的低温ald基SiBCN材料，并开发了优化的隔离剂RIE工艺，以保持低k值并提供与下游工艺的兼容性。该材料已集成到可制造的14nm替代金属栅极(RMG) FinFET基线中，其RO延迟性能提高了约8%，可靠性满足技术要求[4]。在综合材料性能和可靠性评估的基础上，提出了10nm及以上节点的隔离器设计准则。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2015 Symposium on VLSI Technology (VLSI Technology)

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