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2015 Symposium on VLSI Technology (VLSI Technology)最新文献

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14nm FDSOI upgraded device performance for ultra-low voltage operation 14nm FDSOI升级器件性能，实现超低电压工作
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223664
O. Weber, E. Josse, J. Mazurier, N. Degors, S. Chhun, P. Maury, S. Lagrasta, D. Barge, J. Manceau, M. Haond
{"title":"14nm FDSOI upgraded device performance for ultra-low voltage operation","authors":"O. Weber, E. Josse, J. Mazurier, N. Degors, S. Chhun, P. Maury, S. Lagrasta, D. Barge, J. Manceau, M. Haond","doi":"10.1109/VLSIT.2015.7223664","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223664","url":null,"abstract":"A performance upgrade of our 14nm FDSOI technology is reported in this paper. Compared to our previous 14nm FDSOI assessment, a -17% delay at the same leakage is demonstrated. We show that the AC performance of 28nm FDSOI at a 0.9V supply voltage is reached at 0.6V in 14nm FDSOI technology. This corresponds to a 50% increase in frequency at the same dynamic power, or a 65% power saving at the same operation frequency. The transistors are optimized to provide better drive current and, for the first time, a novel SiBCN low-k spacer material is successfully integrated in a gate-first FDSOI technology, providing a 10% reduction in gate-to-source/drain parasitic capacitance.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123508147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A novel CBRAM integration using subtractive dry-etching process of Cu enabling high-performance memory scaling down to 10nm node 一种新型的CBRAM集成，采用Cu的减干蚀刻工艺，使高性能存储器缩小到10nm节点
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223718
A. Redolfi, L. Goux, N. Jossart, F. Yamashita, E. Nishimura, D. Urayama, K. Fujimoto, T. Witters, F. Lazzarino, M. Jurczak
{"title":"A novel CBRAM integration using subtractive dry-etching process of Cu enabling high-performance memory scaling down to 10nm node","authors":"A. Redolfi, L. Goux, N. Jossart, F. Yamashita, E. Nishimura, D. Urayama, K. Fujimoto, T. Witters, F. Lazzarino, M. Jurczak","doi":"10.1109/VLSIT.2015.7223718","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223718","url":null,"abstract":"We introduce for the first time a novel integration scheme of CBRAM cells, where the Cu electrode is patterned using a subtractive dry-etching process. We demonstrate excellent performances of 30nm-size cells (1μs-write at ≤50μA, >106 endurance, excellent retention at 150°C) as well as scaling potential of CBRAM down to 10nm-node using 5nm-thick Cu electrodes.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125501131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Highly reliable TaOx ReRAM with centralized filament for 28-nm embedded application 高度可靠的TaOx ReRAM，具有集中灯丝，适用于28纳米嵌入式应用
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIC.2015.7231381
Y. Hayakawa, A. Himeno, R. Yasuhara, Werner Boullart, E. Vecchio, T. Vandeweyer, Thomas Witters, D. Crotti, Malgorzata Jurczak, S. Fujii, S. Ito, Y. Kawashima, Yuichiro Ikeda, A. Kawahara, K. Kawai, Z. Wei, S. Muraoka, K. Shimakawa, T. Mikawa, S. Yoneda
{"title":"Highly reliable TaOx ReRAM with centralized filament for 28-nm embedded application","authors":"Y. Hayakawa, A. Himeno, R. Yasuhara, Werner Boullart, E. Vecchio, T. Vandeweyer, Thomas Witters, D. Crotti, Malgorzata Jurczak, S. Fujii, S. Ito, Y. Kawashima, Yuichiro Ikeda, A. Kawahara, K. Kawai, Z. Wei, S. Muraoka, K. Shimakawa, T. Mikawa, S. Yoneda","doi":"10.1109/VLSIC.2015.7231381","DOIUrl":"https://doi.org/10.1109/VLSIC.2015.7231381","url":null,"abstract":"For 28-nm embedded application, we have proposed a TaOx-based ReRAM with precise filament positioning and high thermal stability. The cell was realized using several newly-developed process technologies and cell structures: low-damage etching, cell side oxidation and encapsulated cell structure. As a result, we succeeded for the first time in forming a filament at the cell center. In addition, we confirmed the feasibility of 20-nm cell size. Excellent reliability was achieved in 2-Mbit 40-nm ReRAM: 100k cycles and 10 years' retention at 85 °C was demonstrated.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117006934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
The progresses of MRAM as a memory to save energy consumption and its potential for further reduction MRAM作为存储器的节能进展及其进一步降低能耗的潜力
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223638
H. Yoda, E. Kitagawa, N. Shimomura, S. Fujita, M. Amano
{"title":"The progresses of MRAM as a memory to save energy consumption and its potential for further reduction","authors":"H. Yoda, E. Kitagawa, N. Shimomura, S. Fujita, M. Amano","doi":"10.1109/VLSIT.2015.7223638","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223638","url":null,"abstract":"Critical switching current, I<sub>sw</sub>, of STT (Spin Transfer Torque)-MRAM has been reduced by several orders with perpendicular MTJ and the state-of-the-art write charge, Q<sub>w</sub>, becomes the order of 100-150fC. With the small Q<sub>w</sub>, MRAM starts to save energy consumption by 70-80% compared with a conventional memory system. Analysis of the write pulse-width dependence of I<sub>w</sub> revealed a further potential of perpendicular MTJ to reduce I<sub>w</sub> and Q<sub>w</sub>. STT-MRAM is thought to achieve a further reduction of energy consumption.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129412571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Robotics for innovation 机器人创新
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223682
H. Hirukawa
{"title":"Robotics for innovation","authors":"H. Hirukawa","doi":"10.1109/VLSIT.2015.7223682","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223682","url":null,"abstract":"Robotics has been expected to realize innovation by the cost reduction of manufacturing and service delivery for employers, the burden reduction of labors for employees, and the quality upgrade of products and services for their customers. This talk introduces recent trends of robotics for the innovation mainly taking place in Japan. The robots for the cost reduction include industrial robots and autonomous guided vehicles for logistics, those for the burden reduction powered suits and mobile robots, and those for the quality upgrade nursing care robots and personal mobility. The expectations for VLSI technologies are described as well.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125834219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Ultra-low contact resistivity with highly doped Si:P contact for nMOSFET nMOSFET高掺杂Si:P触点超低接触电阻率
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223711
C. Ni, X. Li, S. Sharma, K. V. Rao, M. Jin, C. Lazik, V. Banthia, B. Colombeau, N. Variam, A. Mayur, H. Chung, R. Hung, A. Brand
{"title":"Ultra-low contact resistivity with highly doped Si:P contact for nMOSFET","authors":"C. Ni, X. Li, S. Sharma, K. V. Rao, M. Jin, C. Lazik, V. Banthia, B. Colombeau, N. Variam, A. Mayur, H. Chung, R. Hung, A. Brand","doi":"10.1109/VLSIT.2015.7223711","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223711","url":null,"abstract":"We report a record setting low NMOS contact Rc of 2e-9 Ωcm2 with an all-silicon based solution. The ultra-low contact resistivity of Ti/Si system of 2e-9 Ωcm2 has been demonstrated with Highly Doped Si:P (HD Si:P) EPI layer which is compatible with FinFET S/D structures combined with millisecond laser anneal activation (DSA). Additionally, we show the pathway to further improve contact resistivity with HD Si:P using P implantation followed by laser anneal to reach the contact resistivity requirement for the 10nm or 7 nm nodes.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129998851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
15-nm channel length MoS2 FETs with single- and double-gate structures 15nm通道长度MoS2场效应管，单栅极和双栅极结构
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223690
A. Nourbakhsh, Ahmad Zubair, S. Huang, X. Ling, M. Dresselhaus, J. Kong, S. De Gendt, T. Palacios
{"title":"15-nm channel length MoS2 FETs with single- and double-gate structures","authors":"A. Nourbakhsh, Ahmad Zubair, S. Huang, X. Ling, M. Dresselhaus, J. Kong, S. De Gendt, T. Palacios","doi":"10.1109/VLSIT.2015.7223690","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223690","url":null,"abstract":"We demonstrate single- and double-gated (SG & DG) field effect transistors (FETs) with a record source-drain length (L<sub>S/D</sub>) of 15 nm built on monolayer (t<sub>ch</sub>~0.7 nm) and 4-layer (t<sub>ch</sub>~3 nm) MoS<sub>2</sub> channels using monolayer graphene as the Source/Drain contacts. The best devices, corresponding to DG 4-layer MoS<sub>2</sub>-FETs with L<sub>S/D</sub>=15 nm, had an I<sub>on</sub>/I<sub>off</sub> in excess of 10<sup>6</sup> and a minimum subthreshold swing (SS<sub>min.</sub>) of 90 mV/dec. at V<sub>DS</sub>=0.5 V. At L<sub>S/D</sub>=1 μm and V<sub>DS</sub>=0.5 V, SS<sub>min.</sub>=66 mV/dec., which is the best SS reported in MoS<sub>2</sub> FETs, indicating the high quality of the interface and the enhanced channel electrostatics.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116100960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Further investigations on traps stabilities in random telegraph signal noise and the application to a novel concept physical unclonable function (PUF) with robust reliabilities 随机电报信号噪声中陷阱稳定性的进一步研究及其在鲁棒可靠性物理不可克隆函数(PUF)中的应用
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223695
Jiezhi Chen, T. Tanamoto, H. Noguchi, Y. Mitani
{"title":"Further investigations on traps stabilities in random telegraph signal noise and the application to a novel concept physical unclonable function (PUF) with robust reliabilities","authors":"Jiezhi Chen, T. Tanamoto, H. Noguchi, Y. Mitani","doi":"10.1109/VLSIT.2015.7223695","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223695","url":null,"abstract":"A novel physical unclonable function (PUF) that based on random telegraph signal noise (RTN) is proposed and studied in this work. Firstly, systematical experiments have been done in ultra-scaled devices with various gate stack structures. It is found for the first time that strong correlations between trap time constants and thermal activation energies universally exist in all devices, no matter for hole traps or for electron traps, in high-k dielectrics or in SiO2. More importantly, time constants are stress free and quite stable under electrical stressing. Then, with proposed transient RTN approaches and algorithms, RTN related traps can be detected in a short time and directly utilized in PUF designs. The hamming distance (HD) of intra-PUF and inter-PUF is experimentally characterized, showing excellent endurance properties with no less than 1E6 ID reading cycles.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"451 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116179752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance 硅纳米线CMOS制造与RMG FinFET技术的最小偏差显示创纪录的性能
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIT.2015.7223653
I. Lauer, N. Loubet, S. Kim, J. Ott, S. Mignot, R. Venigalla, T. Yamashita, T. Standaert, J. Faltermeier, V. Basker, B. Doris, M. Guillorn
{"title":"Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance","authors":"I. Lauer, N. Loubet, S. Kim, J. Ott, S. Mignot, R. Venigalla, T. Yamashita, T. Standaert, J. Faltermeier, V. Basker, B. Doris, M. Guillorn","doi":"10.1109/VLSIT.2015.7223653","DOIUrl":"https://doi.org/10.1109/VLSIT.2015.7223653","url":null,"abstract":"We demonstrate a process flow for creating gate-all-around (GAA) Si nanowire (SiNW) MOSFETs with minimal deviation from conventional replacement metal gate (RMG) finFET technology as used in high-volume manufacturing. Using this technique, we demonstrate the highest DC performance shown for GAA SiNW MOSFETs at sub-100 nm gate pitch, and functional high-speed ring oscillators.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116527756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process 低压金属熔断器技术，采用1.6 v可编程1T1R位单元，采用22nm三栅极工艺集成1V电荷泵
2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI: 10.1109/VLSIC.2015.7231372
S. Kulkarni, Zhanping Chen, B. Srinivasan, B. Pedersen, U. Bhattacharya, Kevin Zhang
{"title":"Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process","authors":"S. Kulkarni, Zhanping Chen, B. Srinivasan, B. Pedersen, U. Bhattacharya, Kevin Zhang","doi":"10.1109/VLSIC.2015.7231372","DOIUrl":"https://doi.org/10.1109/VLSIC.2015.7231372","url":null,"abstract":"This work introduces the first high-volume manufacturable metal-fuse technology in a 22nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 16.4μm2 1T1R bit cell is presented that delivers a record low program voltage of 1.6V. This low-voltage operability allows the array to be coupled with logic-voltage power delivery circuits. A charge pump voltage doubler operating on a 1V voltage rail is demonstrated in this paper with healthy fusing yield.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123956935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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