nMOSFET高掺杂Si:P触点超低接触电阻率

2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI:10.1109/VLSIT.2015.7223711

C. Ni, X. Li, S. Sharma, K. V. Rao, M. Jin, C. Lazik, V. Banthia, B. Colombeau, N. Variam, A. Mayur, H. Chung, R. Hung, A. Brand

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引用次数: 35

摘要

我们报告了创纪录的低NMOS接触Rc的2e-9 Ωcm2与全硅基的解决方案。采用高掺杂Si:P (HD Si:P) EPI层，结合毫秒激光退火激活(DSA)技术，与FinFET S/D结构兼容，证明了Ti/Si体系2e-9 Ωcm2的超低接触电阻率。此外，我们展示了进一步提高HD Si:P的接触电阻率的途径，采用P注入，然后激光退火，以达到10nm或7nm节点的接触电阻率要求。

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Ultra-low contact resistivity with highly doped Si:P contact for nMOSFET

We report a record setting low NMOS contact Rc of 2e-9 Ωcm2 with an all-silicon based solution. The ultra-low contact resistivity of Ti/Si system of 2e-9 Ωcm2 has been demonstrated with Highly Doped Si:P (HD Si:P) EPI layer which is compatible with FinFET S/D structures combined with millisecond laser anneal activation (DSA). Additionally, we show the pathway to further improve contact resistivity with HD Si:P using P implantation followed by laser anneal to reach the contact resistivity requirement for the 10nm or 7 nm nodes.

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2015 Symposium on VLSI Technology (VLSI Technology)

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