O. Weber, E. Josse, J. Mazurier, N. Degors, S. Chhun, P. Maury, S. Lagrasta, D. Barge, J. Manceau, M. Haond
{"title":"14nm FDSOI升级器件性能，实现超低电压工作","authors":"O. Weber, E. Josse, J. Mazurier, N. Degors, S. Chhun, P. Maury, S. Lagrasta, D. Barge, J. Manceau, M. Haond","doi":"10.1109/VLSIT.2015.7223664","DOIUrl":null,"url":null,"abstract":"A performance upgrade of our 14nm FDSOI technology is reported in this paper. Compared to our previous 14nm FDSOI assessment, a -17% delay at the same leakage is demonstrated. We show that the AC performance of 28nm FDSOI at a 0.9V supply voltage is reached at 0.6V in 14nm FDSOI technology. This corresponds to a 50% increase in frequency at the same dynamic power, or a 65% power saving at the same operation frequency. The transistors are optimized to provide better drive current and, for the first time, a novel SiBCN low-k spacer material is successfully integrated in a gate-first FDSOI technology, providing a 10% reduction in gate-to-source/drain parasitic capacitance.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"163 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"27","resultStr":"{\"title\":\"14nm FDSOI upgraded device performance for ultra-low voltage operation\",\"authors\":\"O. Weber, E. Josse, J. Mazurier, N. Degors, S. Chhun, P. Maury, S. Lagrasta, D. Barge, J. Manceau, M. Haond\",\"doi\":\"10.1109/VLSIT.2015.7223664\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A performance upgrade of our 14nm FDSOI technology is reported in this paper. Compared to our previous 14nm FDSOI assessment, a -17% delay at the same leakage is demonstrated. We show that the AC performance of 28nm FDSOI at a 0.9V supply voltage is reached at 0.6V in 14nm FDSOI technology. This corresponds to a 50% increase in frequency at the same dynamic power, or a 65% power saving at the same operation frequency. The transistors are optimized to provide better drive current and, for the first time, a novel SiBCN low-k spacer material is successfully integrated in a gate-first FDSOI technology, providing a 10% reduction in gate-to-source/drain parasitic capacitance.\",\"PeriodicalId\":181654,\"journal\":{\"name\":\"2015 Symposium on VLSI Technology (VLSI Technology)\",\"volume\":\"163 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-06-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"27\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 Symposium on VLSI Technology (VLSI Technology)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2015.7223664\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Symposium on VLSI Technology (VLSI Technology)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2015.7223664","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
14nm FDSOI upgraded device performance for ultra-low voltage operation
A performance upgrade of our 14nm FDSOI technology is reported in this paper. Compared to our previous 14nm FDSOI assessment, a -17% delay at the same leakage is demonstrated. We show that the AC performance of 28nm FDSOI at a 0.9V supply voltage is reached at 0.6V in 14nm FDSOI technology. This corresponds to a 50% increase in frequency at the same dynamic power, or a 65% power saving at the same operation frequency. The transistors are optimized to provide better drive current and, for the first time, a novel SiBCN low-k spacer material is successfully integrated in a gate-first FDSOI technology, providing a 10% reduction in gate-to-source/drain parasitic capacitance.
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