A. Redolfi, L. Goux, N. Jossart, F. Yamashita, E. Nishimura, D. Urayama, K. Fujimoto, T. Witters, F. Lazzarino, M. Jurczak
{"title":"A novel CBRAM integration using subtractive dry-etching process of Cu enabling high-performance memory scaling down to 10nm node","authors":"A. Redolfi, L. Goux, N. Jossart, F. Yamashita, E. Nishimura, D. Urayama, K. Fujimoto, T. Witters, F. Lazzarino, M. Jurczak","doi":"10.1109/VLSIT.2015.7223718","DOIUrl":null,"url":null,"abstract":"We introduce for the first time a novel integration scheme of CBRAM cells, where the Cu electrode is patterned using a subtractive dry-etching process. We demonstrate excellent performances of 30nm-size cells (1μs-write at ≤50μA, >106 endurance, excellent retention at 150°C) as well as scaling potential of CBRAM down to 10nm-node using 5nm-thick Cu electrodes.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Symposium on VLSI Technology (VLSI Technology)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2015.7223718","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
We introduce for the first time a novel integration scheme of CBRAM cells, where the Cu electrode is patterned using a subtractive dry-etching process. We demonstrate excellent performances of 30nm-size cells (1μs-write at ≤50μA, >106 endurance, excellent retention at 150°C) as well as scaling potential of CBRAM down to 10nm-node using 5nm-thick Cu electrodes.