50nm 1.2 v geexte1−x/Sb2Te3超晶格拓扑开关随机存取存储器(TRAM)

2015 Symposium on VLSI Technology (VLSI Technology) Pub Date : 2015-06-16 DOI:10.1109/VLSIT.2015.7223707

M. Tai, T. Ohyanagi, M. Kinoshita, T. Morikawa, K. Akita, M. Takato, H. Shirakawa, M. Araidai, K. Shiraishi, N. Takaura

{"title":"50nm 1.2 v geexte1−x/Sb2Te3超晶格拓扑开关随机存取存储器(TRAM)","authors":"M. Tai, T. Ohyanagi, M. Kinoshita, T. Morikawa, K. Akita, M. Takato, H. Shirakawa, M. Araidai, K. Shiraishi, N. Takaura","doi":"10.1109/VLSIT.2015.7223707","DOIUrl":null,"url":null,"abstract":"A 50nm topological-switching random-access memory (TRAM) was fabricated for the first time. A high-quality GexTe1-x/Sb2Te3 superlattice film enabled set and reset voltages of TRAM to be less than 40% of those of PRAM. Statistical analysis of 16kb data showed the reset voltage to be less than 1.2 V, the lowest as a TRAM test chip.","PeriodicalId":181654,"journal":{"name":"2015 Symposium on VLSI Technology (VLSI Technology)","volume":"126 6","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 50-nm 1.2-V GexTe1−x/Sb2Te3 superlattice topological-switching random-access memory (TRAM)\",\"authors\":\"M. Tai, T. Ohyanagi, M. Kinoshita, T. Morikawa, K. Akita, M. Takato, H. Shirakawa, M. Araidai, K. Shiraishi, N. Takaura\",\"doi\":\"10.1109/VLSIT.2015.7223707\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 50nm topological-switching random-access memory (TRAM) was fabricated for the first time. A high-quality GexTe1-x/Sb2Te3 superlattice film enabled set and reset voltages of TRAM to be less than 40% of those of PRAM. Statistical analysis of 16kb data showed the reset voltage to be less than 1.2 V, the lowest as a TRAM test chip.\",\"PeriodicalId\":181654,\"journal\":{\"name\":\"2015 Symposium on VLSI Technology (VLSI Technology)\",\"volume\":\"126 6\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-06-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 Symposium on VLSI Technology (VLSI Technology)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2015.7223707\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Symposium on VLSI Technology (VLSI Technology)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2015.7223707","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

首次制备了50nm拓扑开关随机存取存储器(TRAM)。高质量的geexte1 -x/Sb2Te3超晶格薄膜使TRAM的设置和复位电压小于PRAM的40%。统计分析16kb数据显示复位电压小于1.2 V，为TRAM测试芯片中最低。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 50-nm 1.2-V GexTe1−x/Sb2Te3 superlattice topological-switching random-access memory (TRAM)

A 50nm topological-switching random-access memory (TRAM) was fabricated for the first time. A high-quality Ge_xTe_1-x/Sb₂Te₃ superlattice film enabled set and reset voltages of TRAM to be less than 40% of those of PRAM. Statistical analysis of 16kb data showed the reset voltage to be less than 1.2 V, the lowest as a TRAM test chip.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2015 Symposium on VLSI Technology (VLSI Technology)

自引率

0.00%

发文量