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2017 Symposium on VLSI Circuits最新文献

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High density 3D fanout package for heterogeneous integration 高密度3D风扇包异质集成
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008576
S. Jeng, S. M. Chen, F. Hsu, P. Lin, J. H. Wang, T. Fang, P. Kavle, Y. J. Lin
{"title":"High density 3D fanout package for heterogeneous integration","authors":"S. Jeng, S. M. Chen, F. Hsu, P. Lin, J. H. Wang, T. Fang, P. Kavle, Y. J. Lin","doi":"10.23919/VLSIC.2017.8008576","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008576","url":null,"abstract":"Three-dimensional (3D) fanout package stacking offers new levels of performance, high-density integration, and form factor advantages. Known-good fanout packages are stacked, and the vertical connection is built through Cu pillars in the molding area and solder bumps. Compared to existing TSV-based 3D integrated circuits (3DIC) technology, this solution reduces thermal crosstalk when integrating devices of different die sizes. Fanout package stacking potentially provides a cost-effective platform for highly flexible heterogeneous integration of digital, memory, analog, radio-frequency (RF) and optical devices.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125343426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A CMOS temperature sensor with a 49fJK2 resolution FoM 具有49fJK2分辨率的CMOS温度传感器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008557
S. Pan, Hui Jiang, K. Makinwa
{"title":"A CMOS temperature sensor with a 49fJK2 resolution FoM","authors":"S. Pan, Hui Jiang, K. Makinwa","doi":"10.23919/VLSIC.2017.8008557","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008557","url":null,"abstract":"This paper presents the most energy-efficient CMOS temperature sensor ever reported, with a resolution FoM of 49fJ K2, 2.7× better than the state-of-the-art. It consists of a Wheatstone bridge made from poly-silicon resistors, which is readout by a 2nd-order Continuous-Time Delta-Sigma modulator (CTDSM). This approach leads to a high resolution (160μΚ in 10ms) and a low supply-voltage sensitivity (< 20mK/V at room temperature).","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121803702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Computational locking: Accelerating lock-times in all-digital PLLs 计算锁定:加速全数字锁相环的锁定时间
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008475
Fahim ur Rahman, G. Taylor, V. Sathe
{"title":"Computational locking: Accelerating lock-times in all-digital PLLs","authors":"Fahim ur Rahman, G. Taylor, V. Sathe","doi":"10.23919/VLSIC.2017.8008475","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008475","url":null,"abstract":"We propose computational-lock, a technique for accelerating frequency and phase-acquisition in all-digital PLLs during cold-start and re-lock. A wide-dynamic range, high resolution TDC is also proposed to further support the technique. Resulting lock-time improvements are evaluated through 50,000 repeated measurements of 65nm CMOS test-chips. Mean lock-times of 16Trefcik and 12Trefcik for cold-start and relock respectively are observed. Computational-lock does not impact steady-state PLL power and performance.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115005559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A bio-impedance readout IC with frequency sweeping from 1k-to-1MHz for electrical impedance tomography 一种生物阻抗读出IC，频率扫描范围从1k到1mhz，用于电阻抗断层扫描
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008471
Hyunsoo Ha, M. Konijnenburg, Budi Lukita, Roland van Wegberg, Jiawei Xu, R. van den Hoven, Marijn Lemmens, R. Thoelen, C. van Hoof, N. van Helleputte
{"title":"A bio-impedance readout IC with frequency sweeping from 1k-to-1MHz for electrical impedance tomography","authors":"Hyunsoo Ha, M. Konijnenburg, Budi Lukita, Roland van Wegberg, Jiawei Xu, R. van den Hoven, Marijn Lemmens, R. Thoelen, C. van Hoof, N. van Helleputte","doi":"10.23919/VLSIC.2017.8008471","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008471","url":null,"abstract":"This paper presents a bio-impedance (BIOZ) readout IC for electrical impedance tomography (EIT). The IC includes a complete readout channel for impedance characterization at various frequencies ranging from 1k-to-1MHz, an input multiplexer and a programmable digital controller enabling multi-frequency impedance scanning from multiple locations. To relax the bandwidth requirements of the readout channel, pre-demodulation before the IA is employed. A fast channel settling mechanism (<1ms) allows quick switching between frequencies enabling a fast imaging speed. Dynamic element matching (DEM) in the current generation and chopping in the readout front-end are adopted to mitigate 1/f noise resulting in a noise floor of 38.4mQRMS. This IC, fabricated in 0.18μm, consumes 18.7 μW and 63 μW in the readout front-end and the current generator (CG), respectively. By means of in-vitro and in-vivo testing its effectivity for EIT is demonstrated.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134403719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A 0.028mm2 19.8fJ/step 2nd-order VCO-based CT ΔΣ modulator using an inherent passive integrator and capacitive feedback in 40nm CMOS 采用固有无源积分器和电容反馈的40nm CMOS 0.028mm2 19.8fJ/step二阶vco CT ΔΣ调制器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008538
Shaolan Li, Nan Sun
{"title":"A 0.028mm2 19.8fJ/step 2nd-order VCO-based CT ΔΣ modulator using an inherent passive integrator and capacitive feedback in 40nm CMOS","authors":"Shaolan Li, Nan Sun","doi":"10.23919/VLSIC.2017.8008538","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008538","url":null,"abstract":"This paper presents an OTA-less 2<sup>nd</sup>-order VCO-based CT ΔΣ modulator featuring a passive integrator that makes use of the VCO's inherent parasitic effect. A low-power capacitive feedback technique is also presented for robust loop compensation. Fabricated in 40nm CMOS, the prototype occupies 0.028mm<sup>2</sup> of active area and consumes 524μW when sampling at 330MHz. The ΔΣM achieved peak Walden FoM of 19.8fJ/step with 68.6dB SNDR over 6MHz BW.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114341999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 16.6-pJ/b 150-Mb/s body channel communication transceiver with decision feedback equalization improving >200% area efficiency 采用决策反馈均衡的16.6 pj /b 150 mb /s体信道通信收发器，提高了>200%的面积效率
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008549
Ji-Hoon Lee, Kwangmin Kim, Minsoo Choi, J. Sim, Hong-June Park, Byungsub Kim
{"title":"A 16.6-pJ/b 150-Mb/s body channel communication transceiver with decision feedback equalization improving >200% area efficiency","authors":"Ji-Hoon Lee, Kwangmin Kim, Minsoo Choi, J. Sim, Hong-June Park, Byungsub Kim","doi":"10.23919/VLSIC.2017.8008549","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008549","url":null,"abstract":"This paper presents the fastest and most energy efficient body channel communication transceiver integrated into the smallest chip area. To enhance data rate with limited human body channel bandwidth, decision feedback equalization technique is adopted to body channel communication for the first time. The transceiver, fabricated in 65 nm CMOS technology, reliably (BER < 10−6) achieves the maximum data rates of 150 Mb/s and 100 Mb/s over 20-cm and 1.0 m human body channels at costs of 16.6 pJ/b and 23.5 pJ/b. Even with the drastic performance improvements, the transceiver only occupies an area of 5580 μm2, which is of less than 1% compared to any previously presented works. This remarkable area efficiency verifies the superiority of the proposed design's simplicity of and efficiency.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114585673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 9.1 mW inductive displacement-to-digital converter with 1.85 nm resolution 9.1 mW感应位移-数字转换器，1.85 nm分辨率
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008556
V. Chaturvedi, J. Vogel, K. Makinwa, S. Nihtianov
{"title":"A 9.1 mW inductive displacement-to-digital converter with 1.85 nm resolution","authors":"V. Chaturvedi, J. Vogel, K. Makinwa, S. Nihtianov","doi":"10.23919/VLSIC.2017.8008556","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008556","url":null,"abstract":"A displacement-to-digital converter (DDC) based on inductive (eddy-current) sensor is presented. The sensor is embedded in a self-oscillating front-end, whose 145MHz output is then digitized by a ratiometric ΔΣ ADC. Over a 10μm range, the DDC achieves 1.85nm resolution (1.02 pH), in a 2kHz bandwidth. It draws 9.1mW from a 1.8 V supply making it the most energy-efficient ECS interface ever reported.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129409303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 0.06mm2 ± 50mV range −82dB THD chopper VCO-based sensor readout circuit in 40nm CMOS 基于40nm CMOS的0.06mm2±50mV范围- 82dB THD斩波vco传感器读出电路
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008558
Chih-Chan Tu, Yu-Kai Wang, Tsung-Hsien Lin
{"title":"A 0.06mm2 ± 50mV range −82dB THD chopper VCO-based sensor readout circuit in 40nm CMOS","authors":"Chih-Chan Tu, Yu-Kai Wang, Tsung-Hsien Lin","doi":"10.23919/VLSIC.2017.8008558","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008558","url":null,"abstract":"A VCO-based sensor readout circuit is presented. It comprises a VCO-based integrator with counters, and a capactively-coupled feedback DAC, to form a 1st-order DSM with high input impedance and wide dynamic range for voltage sensors. Chopping is applied to suppress the flicker noise. The time-domain approach relaxes the voltage swing requirement compared to that of a Gm-C integrator, and thus area efficiency is achieved. The prototype is implemented in 40nm CMOS. It consumes 21μA under 1.2V supply. With a 100mVpp sinusoidal input, it achieves 74.9dB SNDR over 2 kHz BW and the THD is −82dB. This readout circuit is also measured with a Hall sensor to demonstrate its operation. The FoM and distortion achieves the state-of-the-art performance of VCO-based sensor readout circuits.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124187381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A compact sensor readout circuit with combined temperature, capacitance and voltage sensing functionality 一个紧凑的传感器读出电路，结合温度，电容和电压传感功能
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008555
B. Yousefzadeh, Wei Wu, B. Buter, K. Makinwa, Michiel Pertijs
{"title":"A compact sensor readout circuit with combined temperature, capacitance and voltage sensing functionality","authors":"B. Yousefzadeh, Wei Wu, B. Buter, K. Makinwa, Michiel Pertijs","doi":"10.23919/VLSIC.2017.8008555","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008555","url":null,"abstract":"This paper presents an area- and energy-efficient sensor readout circuit, which can precisely digitize temperature, capacitance and voltage. The three modes use only on-chip references and employ a shared zoom ADC based on SAR and ΔΣ conversion to save die area. Measurements on 24 samples from a single wafer show a temperature inaccuracy of ±0.2 °C (3σ) over the military temperature range (−55°C to 125°C). The voltage sensing shows an inaccuracy of ±0.5%. The sensor also offers 18.7-ENOB capacitance-to-digital conversion, which handles up to 3.8 pF capacitance with a 0.76 pJ/conv.-step energy-efficiency FoM. It occupies 0.33 mm in a 0.16 μm CMOS process and draws 4.6 μA current from a 1.8 V supply.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"05 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127137782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 2.4GHz, −102dBm-sensitivity, 25kb/s, 0.466mW interference resistant BFSK multi-channel sliding-IF ULP receiver 2.4GHz，−102dbm灵敏度，25kb/s, 0.466mW抗干扰BFSK多通道滑动中频ULP接收机
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008552
Hyun-Gi Seok, Oh-Yong Jung, Anjana Dissanayake, Sang-Gug Lee
{"title":"A 2.4GHz, −102dBm-sensitivity, 25kb/s, 0.466mW interference resistant BFSK multi-channel sliding-IF ULP receiver","authors":"Hyun-Gi Seok, Oh-Yong Jung, Anjana Dissanayake, Sang-Gug Lee","doi":"10.23919/VLSIC.2017.8008552","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008552","url":null,"abstract":"This paper presents an ultra-low power, high-sensitivity, and interference-resistant receiver suitable for IoT applications. By the combination of sliding-IF based low-power down-conversion and relative-power-detection based FSK demodulation, the proposed receiver achieves multi-channel operation and minimizes power consumption. Cascaded N-path filter and 4th-order hybrid-PPF are adopted to improve the sensitivity and carrier-to-interference ratio. Implemented in a 65nm CMOS, the receiver achieves −102dBm sensitivity at 0.1% BER and 25kb/s data rate while consuming 466μW from a 0.6V supply.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127775872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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