A 0.06mm2 ± 50mV range −82dB THD chopper VCO-based sensor readout circuit in 40nm CMOS

Abstract

A VCO-based sensor readout circuit is presented. It comprises a VCO-based integrator with counters, and a capactively-coupled feedback DAC, to form a 1st-order DSM with high input impedance and wide dynamic range for voltage sensors. Chopping is applied to suppress the flicker noise. The time-domain approach relaxes the voltage swing requirement compared to that of a Gm-C integrator, and thus area efficiency is achieved. The prototype is implemented in 40nm CMOS. It consumes 21μA under 1.2V supply. With a 100mVpp sinusoidal input, it achieves 74.9dB SNDR over 2 kHz BW and the THD is −82dB. This readout circuit is also measured with a Hall sensor to demonstrate its operation. The FoM and distortion achieves the state-of-the-art performance of VCO-based sensor readout circuits.