发布求助
文献互助 智能选刊 最新文献

2017 Symposium on VLSI Circuits最新文献

筛选
英文 中文
A 10Gb/s 10mm on-chip serial link in 65nm CMOS featuring a half-rate time-based decision feedback equalizer
2017 Symposium on VLSI Circuits Pub Date : 2017-08-10 DOI: 10.23919/VLSIC.2017.8008546
Po-Wei Chiu, Somnath Kundu, Qianying Tang, C. Kim
{"title":"A 10Gb/s 10mm on-chip serial link in 65nm CMOS featuring a half-rate time-based decision feedback equalizer","authors":"Po-Wei Chiu, Somnath Kundu, Qianying Tang, C. Kim","doi":"10.23919/VLSIC.2017.8008546","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008546","url":null,"abstract":"An all-digital 2-tap half-rate time-based decision feedback equalizer (TB-DFE) was demonstrated on a 10mm on-chip serial link. Implemented in a 65nm GP technology, the transmitter and receiver achieve an energy-efficiency of 31.9 and 45.3 fJ/b/mm, respectively, at a data rate of 10Gb/s. A Bit Error Rate (BER) less than 10−12 was verified for an eye width of 0.43 Unit Interval (UI) using an in-situ BER monitor.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128541431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 42nJ/conversion on-demand state-of-charge indicator for miniature IoT Li-ion batteries 用于微型物联网锂离子电池的42nJ/转换按需充电状态指示器
2017 Symposium on VLSI Circuits Pub Date : 2017-08-10 DOI: 10.23919/VLSIC.2017.8008484
Junwon Jeong, Seokhyeon Jeong, Chulwoo Kim, D. Sylvester, D. Blaauw
{"title":"A 42nJ/conversion on-demand state-of-charge indicator for miniature IoT Li-ion batteries","authors":"Junwon Jeong, Seokhyeon Jeong, Chulwoo Kim, D. Sylvester, D. Blaauw","doi":"10.23919/VLSIC.2017.8008484","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008484","url":null,"abstract":"An energy efficient State-of-Charge (SOC) indication algorithm and integrated system for small IoT batteries are introduced in this paper. The system is implemented in a 180-nm CMOS technology. Based on a key finding that small Li-ion batteries exhibit a linear dependence between battery voltage and load current, we propose an instantaneous linear extrapolation (ILE) algorithm and circuit allowing on-demand estimation of SOC. Power consumption is 42nW and maximum SOC indication error is 1.7%.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122970480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A fully integrated closed-loop neuromodulation SoC with wireless power and bi-directional data telemetry for real-time human epileptic seizure control 一个完全集成的闭环神经调节SoC，具有无线电源和双向数据遥测，用于实时控制人类癫痫发作
2017 Symposium on VLSI Circuits Pub Date : 2017-08-10 DOI: 10.23919/VLSIC.2017.8008541
Cheng-Hsiang Cheng, Ping-Yuan Tsai, Tzu-Yi Yang, Wan-Hsueh Cheng, Ting-Yang Yen, Zhicong Luo, Xin-Hong Qian, Zhi-Xin Chen, T. Lin, Wei-Hong Chen, Wei-Ming Chen, Sheng-Fu Liang, Fu-Zen Shaw, Cheng-Siu Chang, F. Shih, Y. Hsin, Chen-Yi Lee, M. Ker, Chung-Yu Wu
{"title":"A fully integrated closed-loop neuromodulation SoC with wireless power and bi-directional data telemetry for real-time human epileptic seizure control","authors":"Cheng-Hsiang Cheng, Ping-Yuan Tsai, Tzu-Yi Yang, Wan-Hsueh Cheng, Ting-Yang Yen, Zhicong Luo, Xin-Hong Qian, Zhi-Xin Chen, T. Lin, Wei-Hong Chen, Wei-Ming Chen, Sheng-Fu Liang, Fu-Zen Shaw, Cheng-Siu Chang, F. Shih, Y. Hsin, Chen-Yi Lee, M. Ker, Chung-Yu Wu","doi":"10.23919/VLSIC.2017.8008541","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008541","url":null,"abstract":"This paper presents a 16-channel closed-loop neuromodulation SoC for human seizure control. The SoC includes a 16-ch signal acquisition unit, a bio-signal processor, a 16-ch adaptive stimulator, and wireless telemetry. The signal acquisition unit achieves 3.78 NEF and shares electrodes with stimulator. The seizure detection latency is 0.76s and delivered 0.5–3mA biphasic current stimulation. The SoC is powered wirelessly and bidirectional data telemetry is realized through the same pair of coils in 13.56MHz.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123954804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS BRein存储器:一种13层4.2 K神经元/0.8 M突触二/三元可重构内存深度神经网络加速器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008533
Kota Ando, Kodai Ueyoshi, Kentaro Orimo, H. Yonekawa, Shimpei Sato, Hiroki Nakahara, M. Ikebe, T. Asai, Shinya Takamaeda-Yamazaki, T. Kuroda, M. Motomura
{"title":"BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS","authors":"Kota Ando, Kodai Ueyoshi, Kentaro Orimo, H. Yonekawa, Shimpei Sato, Hiroki Nakahara, M. Ikebe, T. Asai, Shinya Takamaeda-Yamazaki, T. Kuroda, M. Motomura","doi":"10.23919/VLSIC.2017.8008533","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008533","url":null,"abstract":"A versatile reconfigurable accelerator for binary/ternary deep neural networks (DNNs) is presented. It features a massively parallel in-memory processing architecture and stores varieties of binary/ternary DNNs with a maximum of 13 layers, 4.2 K neurons, and 0.8 M synapses on chip. The 0.6 W, 1.4 TOPS chip achieves performance and energy efficiency that is 10–10<sup>2</sup> and 10<sup>2</sup>–10<sup>4</sup> times better than a CPU/GPU/FPGA.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125165869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 72
A capacitively-degenerated 100dB linear 20–150MS/s dynamic amplifier 电容退化100dB线性20-150MS /s动态放大器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008459
Md Shakil Akter, K. Makinwa, K. Bult
{"title":"A capacitively-degenerated 100dB linear 20–150MS/s dynamic amplifier","authors":"Md Shakil Akter, K. Makinwa, K. Bult","doi":"10.23919/VLSIC.2017.8008459","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008459","url":null,"abstract":"This paper presents a new dynamic residue amplifier for pipelined ADCs. With an input of 100mVpp, diff and 4x gain, it achieves −100dB THD, the lowest ever reported in dynamic amplifiers. Compared to the state-of-the-art, it exhibits >25dB better linearity with >2x larger output swing and similar noise performance. The key to this is a new linearization technique based on capacitive-degeneration. Fabricated in a 28nm CMOS, the prototype amplifier dissipates 87μW at a clock speed of 43MS/s and maintains −100dB THD up to 150MS/s.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129631619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A single-chip 2048×1080 resolution 32fps 380mW trinocular disparity estimation processor in 28nm CMOS technology 采用28nm CMOS技术的单片2048×1080分辨率32fps 380mW三视视差估计处理器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008489
Jonathan Narinx, T. Demirci, Abdulkadir Akin, Y. Leblebici
{"title":"A single-chip 2048×1080 resolution 32fps 380mW trinocular disparity estimation processor in 28nm CMOS technology","authors":"Jonathan Narinx, T. Demirci, Abdulkadir Akin, Y. Leblebici","doi":"10.23919/VLSIC.2017.8008489","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008489","url":null,"abstract":"This paper presents a single-chip trinocular disparity estimation processor, capable of computing in real-time up to 2048×1080 resolution depth maps at 32fps with up to 256-pixel disparity range using two/three CMOS camera sensors. The most important feature of the presented design is that the chip is based on a trinocular adaptive window matching process that requires very limited on-chip memory, and completely avoids the usage of any external memory. Moreover, it provides the highest reported disparity range capability at the lowest power consumption and highest frame rate, while computing high-quality disparity results. It features a stream-in/out interface to be easily integrated in existing vision systems, without additional overhead, and offers a dynamically scalable tradeoff between throughput, resolution and disparity range. The single-chip is fabricated in 28nm CMOS technology, has a die area of 5.96mm2 and a power consumption of 380mW at 300MHz clock frequency.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114658479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An implantable 700μW 64-channel neuromodulation IC for simultaneous recording and stimulation with rapid artifact recovery 一种可植入的700μW 64通道神经调节IC，用于同时记录和刺激并快速恢复伪影
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008543
Benjamin C. Johnson, S. Gambini, I. Izyumin, Ali Moin, Andy Zhou, George Alexandrov, Samantha R. Santacruz, J. Rabaey, J. Carmena, R. Muller
{"title":"An implantable 700μW 64-channel neuromodulation IC for simultaneous recording and stimulation with rapid artifact recovery","authors":"Benjamin C. Johnson, S. Gambini, I. Izyumin, Ali Moin, Andy Zhou, George Alexandrov, Samantha R. Santacruz, J. Rabaey, J. Carmena, R. Muller","doi":"10.23919/VLSIC.2017.8008543","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008543","url":null,"abstract":"We present an 180nm HV CMOS IC for concurrent neural stimulation and recording that combines 64 low-noise recording front-ends and 4 independent stimulators multiplexed to any of the 64 channels. The stimulators have 5mA peak current, 12V compliance and dynamic power management to maximize efficiency. Co-design of the stimulation and recording subsystems resulted in 100mV of recording linear range, 70nV/rtHz noise, and a rapid 1ms (single-sample) artifact recovery during stimulation.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116254098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 97
A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications 用于深度学习应用的1.06- 5.09 TOPS/W可重构混合神经网络处理器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008534
S. Yin, Ouyang Peng, Shibin Tang, Fengbin Tu, Xiudong Li, Leibo Liu, Shaojun Wei
{"title":"A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications","authors":"S. Yin, Ouyang Peng, Shibin Tang, Fengbin Tu, Xiudong Li, Leibo Liu, Shaojun Wei","doi":"10.23919/VLSIC.2017.8008534","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008534","url":null,"abstract":"An energy-efficient hybrid neural network (NN) processor is implemented in a 65nm technology. It has two 16×16 reconfigurable heterogeneous processing elements (PEs)arrays. To accelerate a hybrid-NN, the PE array is designed to support on demand partitioning and reconfiguration for parallel processing different NNs. To improve energy efficiency, each PE supports bit-width adaptive computing to meet variant bit-width of different neural layers. Measurement results show that this processor achieves a peak 409.6GOPS running at 200MHz and at most 5.09TOPS/W energy efficiency. This processor outperforms the state-of-the-art up to 5.2X in energy efficiency.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123440679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 70
A calibration-free 2.3 mW 73.2 dB SNDR 15b 100 MS/s four-stage fully differential ring amplifier based SAR-assisted pipeline ADC 基于sar辅助管路ADC的免校准2.3 mW 73.2 dB SNDR 15b 100 MS/s 4级全差分环放大器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008562
Yong Lim, M. Flynn
{"title":"A calibration-free 2.3 mW 73.2 dB SNDR 15b 100 MS/s four-stage fully differential ring amplifier based SAR-assisted pipeline ADC","authors":"Yong Lim, M. Flynn","doi":"10.23919/VLSIC.2017.8008562","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008562","url":null,"abstract":"A four-stage fully differential ring amplifier in 40 nm CMOS improves gain to over 90 dB without compromising speed. It is applied in a 15b, 100 MS/s calibration-free SAR-assisted pipeline ADC. In addition, a new auto-zero noise filtering method reduces noise without consuming additional power. The ADC achieves 73.2 dB SNDR (11.9b) and 90.4 dB SFDR with a 1.1 V supply. It consumes 2.3 mW resulting in a SNDR based Schreier FoM of 176.6 dB.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"389 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129657046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Recryptor: A reconfigurable in-memory cryptographic Cortex-M0 processor for IoT Recryptor:用于物联网的可重构内存加密Cortex-M0处理器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008501
Yiqun Zhang, Li Xu, Kaiyuan Yang, Qing Dong, Supreet Jeloka, D. Blaauw, D. Sylvester
{"title":"Recryptor: A reconfigurable in-memory cryptographic Cortex-M0 processor for IoT","authors":"Yiqun Zhang, Li Xu, Kaiyuan Yang, Qing Dong, Supreet Jeloka, D. Blaauw, D. Sylvester","doi":"10.23919/VLSIC.2017.8008501","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008501","url":null,"abstract":"This paper proposes Recryptor, an energy efficient and compact ARM Cortex-M0 based reconfigurable cryptographic processor using in-memory computing. Recryptor is capable of accelerating a wide range of cryptography algorithms and standards, including public/private key cryptography and hash functions, by augmenting the memory of a commercial general purpose IoT processor resulting in a highly compact implementation. The wide bit-width of memory is ideally suited for high bitwidth (64–512b) arithmetic operations common in cryptographic functions. Recryptor (28.8 MHz at 0.7 V) achieves 6.8× average speedup and 12.8× average energy improvements over state-of-the-art software and hardware-accelerated implementations with only 0.128 mm2 area overhead in 40nm CMOS.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122969274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信