{"title":"A 10Gb/s 10mm on-chip serial link in 65nm CMOS featuring a half-rate time-based decision feedback equalizer","authors":"Po-Wei Chiu, Somnath Kundu, Qianying Tang, C. Kim","doi":"10.23919/VLSIC.2017.8008546","DOIUrl":null,"url":null,"abstract":"An all-digital 2-tap half-rate time-based decision feedback equalizer (TB-DFE) was demonstrated on a 10mm on-chip serial link. Implemented in a 65nm GP technology, the transmitter and receiver achieve an energy-efficiency of 31.9 and 45.3 fJ/b/mm, respectively, at a data rate of 10Gb/s. A Bit Error Rate (BER) less than 10−12 was verified for an eye width of 0.43 Unit Interval (UI) using an in-situ BER monitor.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"117 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2017.8008546","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 10Gb/s 10mm on-chip serial link in 65nm CMOS featuring a half-rate time-based decision feedback equalizer
An all-digital 2-tap half-rate time-based decision feedback equalizer (TB-DFE) was demonstrated on a 10mm on-chip serial link. Implemented in a 65nm GP technology, the transmitter and receiver achieve an energy-efficiency of 31.9 and 45.3 fJ/b/mm, respectively, at a data rate of 10Gb/s. A Bit Error Rate (BER) less than 10−12 was verified for an eye width of 0.43 Unit Interval (UI) using an in-situ BER monitor.
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