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2017 Symposium on VLSI Circuits最新文献

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A 20nW-to-140mW input power range, 94% peak efficiency energy-harvesting battery charger with frequency-sweeping input voltage monitor and optimal on-time generator 20nw - 140mw输入功率范围，94%峰值效率的能量收集电池充电器，带扫频输入电压监视器和最佳准时发电机
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008483
Sung-Youb Jung, Minbok Lee, Joonseok Yang, Jaeha Kim
{"title":"A 20nW-to-140mW input power range, 94% peak efficiency energy-harvesting battery charger with frequency-sweeping input voltage monitor and optimal on-time generator","authors":"Sung-Youb Jung, Minbok Lee, Joonseok Yang, Jaeha Kim","doi":"10.23919/VLSIC.2017.8008483","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008483","url":null,"abstract":"This paper presents a boost-type energy-harvesting battery charger IC that can maintain high efficiencies over a wide range of input power. In other words, the IC has a fast response to achieve 94% peak efficiency at high input power conditions, yet dissipates only 14.7nW quiescent power to achieve a net positive charging at low input power conditions. The key to this fast, low-power operation is the use of frequency-sweeping input voltage monitor, i.e., a clocked comparator of which sampling clock frequency is exponentially swept from 800-kHz to 100-Hz. In addition, an optimal on-time pulse generator improves the power efficiency by scaling the switching pulse-width proportional to the battery-to-input voltage ratio. The prototype IC fabricated in 0.25-μm CMOS can charge a 3.0V battery from the input source ranging 0.3–2V and 20nW–140mW, which is the widest input power range reported to date.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129676631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 16nm 69dB SNDR 300MSps ADC with capacitive reference stabilization 具有电容基准稳定的16nm 69dB SNDR 300MSps ADC
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008559
E. Martens, B. Hershberg, J. Craninckx
{"title":"A 16nm 69dB SNDR 300MSps ADC with capacitive reference stabilization","authors":"E. Martens, B. Hershberg, J. Craninckx","doi":"10.23919/VLSIC.2017.8008559","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008559","url":null,"abstract":"We present a 300 MSps 2 times interleaved pipelined SAR ADC in 16nm digital CMOS. It implements a new scheme to cancel reference voltage ripple due to DAC switching, greatly reducing requirements for decoupling capacitance and/or reference buffering, and achieves better than 76dB harmonic distortion. At 300 MSps, the peak ENOB is 11.2 bit with a power consumption of 3.6mW.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123751058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 5Gb/s 7.1fJ/b/mm 8× multi-drop on-chip 10mm data link in 14nm FinFET CMOS SOI at 0.5V 5Gb/s 7.1fJ/b/mm 8×多滴片上10mm数据链路，采用14nm FinFET CMOS SOI，电压0.5V
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008545
E. Sacco, P. Francese, M. Brändli, C. Menolfi, T. Morf, A. Cevrero, I. Ozkaya, M. Kossel, L. Kull, D. Luu, Hazar Yueksel, G. Gielen, T. Toifl
{"title":"A 5Gb/s 7.1fJ/b/mm 8× multi-drop on-chip 10mm data link in 14nm FinFET CMOS SOI at 0.5V","authors":"E. Sacco, P. Francese, M. Brändli, C. Menolfi, T. Morf, A. Cevrero, I. Ozkaya, M. Kossel, L. Kull, D. Luu, Hazar Yueksel, G. Gielen, T. Toifl","doi":"10.23919/VLSIC.2017.8008545","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008545","url":null,"abstract":"We report a 5Gb/s data link implemented in 14nm FinFET CMOS SOI technology in which a single transmitter (TX) broadcasts NRZ data to eight receivers (RXs) distributed along an on-chip RC-dominated 10mm-long channel. The TX comprises a full-rate AC-coupled 2-tap FIR driver with a quarter-rate pre-driver. Each RX is equipped with a novel decision-gated 1-tap speculative DFE optimized for low-power. The RX architecture is half-rate and sliced data are de-multiplexed at quarter-rate. PRBS generator and checker are available on-chip. Correct operation was verified with PRBS31 data transmitted at 5Gb/s and concurrently received error-free at each drop with >40% horizontal margin (BER<10−12). At this data-rate the efficiency is 7.1fJ/b/mm' resulting in the best performance among multi-drop on-chip data links so far published (to the best of our knowledge). The TX and eight RXs are running on a 0.5 V power supply and consume 0.62 and 0.98mW' respectively.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125124760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 36μW reconfigurable analog front-end IC for multimodal vital signs monitoring 用于多模态生命体征监测的36μW可重构模拟前端IC
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008469
Jiawei Xu, M. Konijnenburg, Hyunsoo Ha, Roland van Wegberg, Budi Lukita, Samira Zali Asl, C. van Hoof, N. van Helleputte
{"title":"A 36μW reconfigurable analog front-end IC for multimodal vital signs monitoring","authors":"Jiawei Xu, M. Konijnenburg, Hyunsoo Ha, Roland van Wegberg, Budi Lukita, Samira Zali Asl, C. van Hoof, N. van Helleputte","doi":"10.23919/VLSIC.2017.8008469","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008469","url":null,"abstract":"This paper presents a highly reconfigurable analog front-end (AFE) IC supporting multi-modal (bio)signal monitoring. By efficiently reusing core components, the reconfigurable AFE channel occupies an area of 1.1mm2 while supporting four acquisition modes, i.e. biopotential (ExG), bio-impedance (BioZ), galvanic skin response (GSR) and general purpose analog (GPA). State-of-the-art sensitivity has been achieved at low power by employing both chopping and dynamic element matching (DEM). The reconfigurable AFE channel consumes 36μW maximum from a 1.2 V supply.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125836105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 130nm FeRAM-based parallel recovery nonvolatile SOC for normally-OFF operations with 3.9× faster running speed and 11× higher energy efficiency using fast power-on detection and nonvolatile radio controller 基于130nm feram的并行恢复非易失性SOC，采用快速上电检测和非易失性无线电控制器，可实现正常关闭操作，运行速度提高3.9倍，能效提高11倍
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008531
Zhibo Wang, Fang Su, Yiqun Wang, Zewei Li, Xueqing Li, Ryuji Yoshimura, Takashi Naiki, Takashi Tsuwa, Takahiko Saito, Zhongjun Wang, Koji Taniuchi, Meng-Fan Chang, Huazhong Yang, Yongpan Liu
{"title":"A 130nm FeRAM-based parallel recovery nonvolatile SOC for normally-OFF operations with 3.9× faster running speed and 11× higher energy efficiency using fast power-on detection and nonvolatile radio controller","authors":"Zhibo Wang, Fang Su, Yiqun Wang, Zewei Li, Xueqing Li, Ryuji Yoshimura, Takashi Naiki, Takashi Tsuwa, Takahiko Saito, Zhongjun Wang, Koji Taniuchi, Meng-Fan Chang, Huazhong Yang, Yongpan Liu","doi":"10.23919/VLSIC.2017.8008531","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008531","url":null,"abstract":"This paper proposes a FeRAM-based Nonvolatile SOC (NVSOC) to obtain system-level startup acceleration and energy efficiency enhancement for normally-off applications. The NVSOC supports adaptive parallel recovery and two fast startup schemes. The quick power-on detection is enabled by hysteresis-comparator based voltage detector and leakage cutoff controller. A nonvolatile radio frequency controller (NVRF) is first proposed to further boost the recovery of transceivers. Compared with the fastest switching nonvolatile processor based platform, measurement results show NVSOC achieves 3.9× faster running speed and 11× higher energy efficiency to execute periodical normally-off sensing and transmitting tasks. This is the first parallel recovery enabled NVSOC with fast power-on detection and RF initialization capability.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116744208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 0.3–0.86V fully integrated buck regulator with 2GHz resonant switching for ultra-low power applications 一款0.3-0.86V全集成降压稳压器，具有2GHz谐振开关，适用于超低功耗应用
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008485
Tianyu Jia, Jie Gu
{"title":"A 0.3–0.86V fully integrated buck regulator with 2GHz resonant switching for ultra-low power applications","authors":"Tianyu Jia, Jie Gu","doi":"10.23919/VLSIC.2017.8008485","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008485","url":null,"abstract":"A fully integrated buck regulator for ultra-low voltage application is presented featuring (1) an ultra-high switching frequency at 2GHz with small inductor size at low load current and (2) a resonant switching technique rendering significant efficiency improvement. With small on-chip inductors, the test chip shows a wide voltage tuning range of 0.3–0.86V, at 10–40mA low current, up to 73% efficiency and only occupies 0.073mm2 in a 65nm CMOS process.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129358905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Statistical characterization of radiation-induced pulse waveforms and flip-flop soft errors in 14nm tri-gate CMOS using a back-sampling chain (BSC) technique 利用反采样链(BSC)技术统计表征14nm三栅极CMOS的辐射诱发脉冲波形和触发器软误差
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008570
Saurabh Kumar, M. Cho, Luke Eversen, Hoonki Kim, Qianying Tang, Paul R. Mazanec, P. Meinerzhagen, Andres F. Malavasi, D. Lake, Carlos Tokunaga, H. Quinn, M. Khellah, J. Tschanz, S. Borkar, V. De, C. Kim
{"title":"Statistical characterization of radiation-induced pulse waveforms and flip-flop soft errors in 14nm tri-gate CMOS using a back-sampling chain (BSC) technique","authors":"Saurabh Kumar, M. Cho, Luke Eversen, Hoonki Kim, Qianying Tang, Paul R. Mazanec, P. Meinerzhagen, Andres F. Malavasi, D. Lake, Carlos Tokunaga, H. Quinn, M. Khellah, J. Tschanz, S. Borkar, V. De, C. Kim","doi":"10.23919/VLSIC.2017.8008570","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008570","url":null,"abstract":"A novel BSC circuit with tunable current starved buffers demonstrates higher sensitivity, scalability & accurate statistical characterization of radiation-induced SET pulse waveforms & flip-flop SER in 14nm tri-gate CMOS, thus enabling improved SER estimation & analysis for a range of supply voltages including NTV.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"695 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133704947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 32Gb/s, 4.7pJ/bit optical link with −11.7dBm sensitivity in 14nm FinFET CMOS 一个32Gb/s, 4.7pJ/bit，灵敏度为- 11.7dBm的14nm FinFET CMOS光链路
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008523
J. Proesel, Z. Deniz, A. Cevrero, I. Ozkaya, Seongwon Kim, D. Kuchta, Sungjae Lee, S. Rylov, H. Ainspan, T. Dickson, J. Bulzacchelli, M. Meghelli
{"title":"A 32Gb/s, 4.7pJ/bit optical link with −11.7dBm sensitivity in 14nm FinFET CMOS","authors":"J. Proesel, Z. Deniz, A. Cevrero, I. Ozkaya, Seongwon Kim, D. Kuchta, Sungjae Lee, S. Rylov, H. Ainspan, T. Dickson, J. Bulzacchelli, M. Meghelli","doi":"10.23919/VLSIC.2017.8008523","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008523","url":null,"abstract":"This work presents an 850nm VCSEL-based multi-mode 32Gb/s NRZ optical link with circuits in 14nm bulk FinFET CMOS. The TX uses a 3-tap, 12-Ul-spaced FFE to improve eye opening. The RX uses a low-BW, low-noise TIA and a speculative 1-tap DFE for high sensitivity. The TX and RX power efficiencies are 3.3 and 1.4pJ/bit, respectively. The link sensitivity is −11.7dBm OMA at BER=10\"12 with PRBS31 data.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130440484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
System architecture with single chip 8K HEVC decoder for 8K advanced BS receiver system 系统架构采用单片8K HEVC解码器，用于8K高级BS接收系统
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008487
M. Nakajima, Daisuke Murakami, Hironori Kubo, Takahide Baba, Y. Miki
{"title":"System architecture with single chip 8K HEVC decoder for 8K advanced BS receiver system","authors":"M. Nakajima, Daisuke Murakami, Hironori Kubo, Takahide Baba, Y. Miki","doi":"10.23919/VLSIC.2017.8008487","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008487","url":null,"abstract":"To implement 8K Advanced BS receiver system, 8K HEVC decoder SoC is developed as key component. To solve the exceeded required memory bandwidth over physical memory bandwidth limitation issue for realizing 8K decoder, two types of multi-cast write back scheme, including reference data multi-cast write back and output data multi-cast write back, are introduced. 8K HEVC decoder chip is fabricated in 28nm CMOS technology and SIP packaged with eight DDR3 memories.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"127 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131337650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 10.1" 56-channel, 183 uW/electrode, 0.73 mm2/sensor high SNR 3D hover sensor based on enhanced signal refining and fine error calibrating techniques 基于增强信号精炼和精细误差校准技术的10.1“56通道，183 uW/电极，0.73 mm2/传感器高信噪比3D悬停传感器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008519
Yeunhee Huh, Sung-Wan Hong, Sang-Hui Park, Jun-Suk Bang, Changbyung Park, Sungsoo Park, Hui-Dong Gwon, Se-un Shin, Hongsuk Shin, Sung-Won Choi, Yong-Min Ju, Ji-Hun Lee, G. Cho
{"title":"A 10.1\" 56-channel, 183 uW/electrode, 0.73 mm2/sensor high SNR 3D hover sensor based on enhanced signal refining and fine error calibrating techniques","authors":"Yeunhee Huh, Sung-Wan Hong, Sang-Hui Park, Jun-Suk Bang, Changbyung Park, Sungsoo Park, Hui-Dong Gwon, Se-un Shin, Hongsuk Shin, Sung-Won Choi, Yong-Min Ju, Ji-Hun Lee, G. Cho","doi":"10.23919/VLSIC.2017.8008519","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008519","url":null,"abstract":"This paper presents a high SNR self-capacitance sensing 3D hover sensor that does not use panel offset cancelation blocks. Not only reducing noise components, but increasing the signal components together, this paper achieved a high SNR performance while consuming very low power and die-area. Thanks to the proposed separated structure between driving and sensing circuits of the self-capacitance sensing scheme (SCSS), the signal components are increased without using high-voltage MOS sensing amplifiers which consume big die-area and power and badly degrade SNR. In addition, since a huge panel offset problem in SCSS is solved exploiting the panel's natural characteristics, other costly resources are not required. Furthermore, display noise and parasitic capacitance mismatch errors are compressed. We demonstrate a 39dB SNR at a 1cm hover point under 240Hz scan rate condition with noise experiments, while consuming 183uW/electrode and 0.73mm2/sensor, which are the power per electrode and the die-area per sensor, respectively.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131652721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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