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2017 Symposium on VLSI Circuits最新文献

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A 65nm CMOS I/Q RF power DAC with 24–42dB 3rd harmonic cancellation and up to 18dB mixed-signal filtering 65nm CMOS I/Q射频功率DAC，具有24-42dB三次谐波抵消和高达18dB混合信号滤波
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008517
Bonjern Yang, Eric Y. Chang, A. Niknejad, B. Nikolić, E. Alon
{"title":"A 65nm CMOS I/Q RF power DAC with 24–42dB 3rd harmonic cancellation and up to 18dB mixed-signal filtering","authors":"Bonjern Yang, Eric Y. Chang, A. Niknejad, B. Nikolić, E. Alon","doi":"10.23919/VLSIC.2017.8008517","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008517","url":null,"abstract":"This paper presents an RF DAC transmitter (TX) with integrated, programmable harmonic cancellation as well as mixed-signal filtering at a peak power of 25.6dBm. The 65nm CMOS prototype uses device stacking and transformer combining and demonstrates 24dB to 42dB HD3 reduction across a frequency range of 0.7GHz to 2GHz, and up to 18dB of notching at a 40MHz offset.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123980162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An imager using 2-D single-photon avalanche diode array in 0.18-μm CMOS for automotive LIDAR application 一种应用于汽车激光雷达的0.18 μm CMOS二维单光子雪崩二极管阵列成像仪
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008512
H. Akita, Isamu Takai, K. Azuma, Takehiro Hata, Noriyuki Ozaki
{"title":"An imager using 2-D single-photon avalanche diode array in 0.18-μm CMOS for automotive LIDAR application","authors":"H. Akita, Isamu Takai, K. Azuma, Takehiro Hata, Noriyuki Ozaki","doi":"10.23919/VLSIC.2017.8008512","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008512","url":null,"abstract":"A feasibility imager chip of a 32× 4-pixel array was developed in a 0.18-μm CMOS process for a small size automotive laser imaging detection and ranging. Each pixel consists of 8 single-photon avalanche diodes as a world-first 2-D pixel array with digital output macro pixel architecture which enables laser signal sensing under sunlight noise. Distance measurement results show less than 2.1% nonlinearity and 0.11-m standard deviation up to 20-m distance with 10%-refIective target under the ambient light of 75 klux.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116346648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Innovative solutions toward future society with AI, Robotics, and IoT 人工智能、机器人、物联网等面向未来社会的创新解决方案
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008499
T. Yukitake
{"title":"Innovative solutions toward future society with AI, Robotics, and IoT","authors":"T. Yukitake","doi":"10.23919/VLSIC.2017.8008499","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008499","url":null,"abstract":"AI, Robotics, and loT are attracting wide attention, expected as technologies to change society in the future. These innovative technologies have potentials to build (1) a borderless communication society, (2) a symbiotic society between humans and robots, and (3) a safe and secure networked society. This paper describes some specific solutions by Panasonic: (1) automatic translation solution, (2) dam inspection robot solution, and (3) large-scale imaging security solution. All of these solutions will work in collaboration with cloud and will evolve into an advanced system. In addition, higher performance and more intelligent processing is required on the IoT/Edge devices, thus VLSI plays even more important roles.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116374778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 230–260GHz wideband amplifier in 65nm CMOS based on dual-peak Gmax-core 一种基于双峰gmax核的65nm CMOS 230-260GHz宽带放大器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008516
Dae-Woong Park, Dzuhri Radityo Utomo, Jong-Phil Hong, Sang-Gug Lee
{"title":"A 230–260GHz wideband amplifier in 65nm CMOS based on dual-peak Gmax-core","authors":"Dae-Woong Park, Dzuhri Radityo Utomo, Jong-Phil Hong, Sang-Gug Lee","doi":"10.23919/VLSIC.2017.8008516","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008516","url":null,"abstract":"A dual-peak maximum achievable gain core design technique is proposed. It has been adopted into a 4-stage wideband amplifier. Implemented in a 65nm CMOS, the amplifier achieves 3dB bandwidth of 30GHz (230∼260GHz), gain of 12.4±1.5dB, and peak PAE of 1.6% while dissipating 23.8mW, which corresponds to the widest bandwidth and highest gain per stage among other reported CMOS amplifiers operating above 200GHz.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125422637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 107 dB SFDR, 80 kS/s Nyquist-rate SAR ADC using a hybrid capacitive and incremental ΣΔ DAC 一个107 dB SFDR, 80 kS/s奈奎斯特速率SAR ADC，采用混合电容式和增量式ΣΔ DAC
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008494
Ahmad AlMarashli, J. Anders, J. Becker, M. Ortmanns
{"title":"A 107 dB SFDR, 80 kS/s Nyquist-rate SAR ADC using a hybrid capacitive and incremental ΣΔ DAC","authors":"Ahmad AlMarashli, J. Anders, J. Becker, M. Ortmanns","doi":"10.23919/VLSIC.2017.8008494","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008494","url":null,"abstract":"This paper introduces an architecture and design for high resolution, high linearity Nyquist rate SAR ADCs requiring only a single simple calibration at startup. The proposed architecture benefits from an intrinsically linear 1.5 bit ΣΔ DAC to resolve the fine bits of the SAR ADC after a coarse conversion phase with a monotonically switched capacitive DAC. The ΣΔ DAC is also used for a single shot calibration of the coarse CDAC which therefore does not require good matching and can be sized solely upon noise requirements. A prototype was fabricated in 40 nm CMOS, with power supplies of 1.1 V and 2.5 V. It occupies an active area of only 0.074mm2. The prototype achieves a measured peak SFDR of 107 dB and a noise limited SNDR of 84.8 dB at 80 kS/s Nyquist rate operation. The core power consumption is 101 μW at 80 kS/s. In oversampling mode, the ADC achieves an SNDR above 90 dB over a 5 kHz bandwidth.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125734276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Strong subthreshold current array PUF with 265 challenge-response pairs resilient to machine learning attacks in 130nm CMOS 具有265个挑战响应对的强亚阈值电流阵列PUF，可抵御130nm CMOS中的机器学习攻击
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008503
Xiaodan Xi, Haoyu Zhuang, Nan Sun, M. Orshansky
{"title":"Strong subthreshold current array PUF with 265 challenge-response pairs resilient to machine learning attacks in 130nm CMOS","authors":"Xiaodan Xi, Haoyu Zhuang, Nan Sun, M. Orshansky","doi":"10.23919/VLSIC.2017.8008503","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008503","url":null,"abstract":"This paper presents a strong silicon physically unclonable function (PUF) immune to machine learning (ML) attacks. The PUF, termed the subthreshold current array (SCA) PUF, is composed of a pair of two-dimensional transistor arrays and a low-offset comparator. The fabricated PUF chip allows 265 challenge-response pairs (CRPs) and achieves high reliability with average bit error rate (BER) of 5.8% for temperatures −20 to 80°C and Vdd + 10%. The calibration-based CRPs filtering method effectively improves BER to 2.6% with a 10% loss of CRPs. When subjected to ML attacks, the PUF shows resilience that is 100X higher than known alternatives, with negligible loss in PUF unpredictability.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128878328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
Intraneural active probe for bidirectional peripheral nerve interface 神经内主动探头用于双向外周神经界面
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008544
M. Ballini, Joonsung Bae, N. Marrocco, R. Verplancke, D. Schaubroeck, D. Cuypers, M. Cauwe, J. O'Callaghan, Ahmed Fahmy, N. Maghari, R. Bashirullah, C. van Hoof, N. van Helleputte, M. O. de Beeck, D. Braeken, S. Mitra
{"title":"Intraneural active probe for bidirectional peripheral nerve interface","authors":"M. Ballini, Joonsung Bae, N. Marrocco, R. Verplancke, D. Schaubroeck, D. Cuypers, M. Cauwe, J. O'Callaghan, Ahmed Fahmy, N. Maghari, R. Bashirullah, C. van Hoof, N. van Helleputte, M. O. de Beeck, D. Braeken, S. Mitra","doi":"10.23919/VLSIC.2017.8008544","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008544","url":null,"abstract":"Advanced bionic prosthetics that can restore both the motor functionality and sensory perception of an amputee, require high-resolution recording and stimulation interfaces targeting the peripheral nervous system (PNS). To provide high nerve fiber selectivity, we propose a low-noise (3.67μVrms) low-power (2.24mW) and high-density CMOS microelectrode probe for intra-neural implantation. The probe is composed of two ICs, encapsulated in a biocompatible and hermetic package, each featuring 64 recording and 16 stimulation electrodes. A backend IC digitizes the recorded signals at 31.25kS/s and provides spike detection.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129021127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A digitally controlled fully integrated voltage regulator with 3D-TSV based on-die solenoid inductor with backside planar magnetic core in 14nm tri-gate CMOS 基于3D-TSV的片上电磁电感，背面为平面磁芯，采用14nm三栅极CMOS
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008574
H. Krishnamurthy, Sheldon Weng, G. Matthew, Ruchir Saraswat, K. Ravichandran, J. Tschanz, V. De
{"title":"A digitally controlled fully integrated voltage regulator with 3D-TSV based on-die solenoid inductor with backside planar magnetic core in 14nm tri-gate CMOS","authors":"H. Krishnamurthy, Sheldon Weng, G. Matthew, Ruchir Saraswat, K. Ravichandran, J. Tschanz, V. De","doi":"10.23919/VLSIC.2017.8008574","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008574","url":null,"abstract":"A fully integrated digitally controlled buck VR, featuring hysteretic and PFM control for maximum light load efficiency, with 3D-TSV based on-die solenoid inductor with backside planar magnetic core in 14nm tri-gate CMOS demonstrates 111 nH/mm2 inductance density & 80% conversion efficiency.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117329972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 28.05Gb/s transceiver using quarter-rate triple-speculation hybrid-DFE receiver with calibrated sampling phases in 32nm CMOS 采用四分之一速率三推测混合dfe接收机的28.05Gb/s收发器，在32nm CMOS中校准采样相位
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008527
G. Gangasani, J. Bulzacchelli, M. Wielgos, W. Kelly, Vivek Sharma, A. Prati, G. Cervelli, Daniele Gardellini, Matthew Baecher, M. Shannon, T. Beukema, Jon Garlett, H. H. Xu, T. Toifl, M. Meghelli, J. Ewen, D. Storaska
{"title":"A 28.05Gb/s transceiver using quarter-rate triple-speculation hybrid-DFE receiver with calibrated sampling phases in 32nm CMOS","authors":"G. Gangasani, J. Bulzacchelli, M. Wielgos, W. Kelly, Vivek Sharma, A. Prati, G. Cervelli, Daniele Gardellini, Matthew Baecher, M. Shannon, T. Beukema, Jon Garlett, H. H. Xu, T. Toifl, M. Meghelli, J. Ewen, D. Storaska","doi":"10.23919/VLSIC.2017.8008527","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008527","url":null,"abstract":"This paper presents a 28.05Gb/s transceiver in 32nm SOI CMOS technology. The receiver employs a quarterrate triple-speculation architecture. Techniques are introduced to adapt for mismatches in tap weights, gains and sampling phases. Error-free signaling at 28.05Gb/s is demonstrated with the transceiver over a 48dB loss backplane channel. In a four-port configuration, the power consumption at 28.05Gb/s is 484mW/lane, giving a FOM of 0.36mW/Gb/s/dB.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"276 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114529307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor 2.5ns延时0.39pJ/b 289μm2/Gb/s超轻量级PRINCE密码处理器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008502
N. Miura, Kohei Matsuda, M. Nagata, S. Bhasin, Ville Yli-Mayry, N. Homma, Y. Mathieu, T. Graba, J. Danger
{"title":"A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor","authors":"N. Miura, Kohei Matsuda, M. Nagata, S. Bhasin, Ville Yli-Mayry, N. Homma, Y. Mathieu, T. Graba, J. Danger","doi":"10.23919/VLSIC.2017.8008502","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008502","url":null,"abstract":"An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131658920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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