N. Miura, Kohei Matsuda, M. Nagata, S. Bhasin, Ville Yli-Mayry, N. Homma, Y. Mathieu, T. Graba, J. Danger
{"title":"2.5ns延时0.39pJ/b 289μm2/Gb/s超轻量级PRINCE密码处理器","authors":"N. Miura, Kohei Matsuda, M. Nagata, S. Bhasin, Ville Yli-Mayry, N. Homma, Y. Mathieu, T. Graba, J. Danger","doi":"10.23919/VLSIC.2017.8008502","DOIUrl":null,"url":null,"abstract":"An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"126 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor\",\"authors\":\"N. Miura, Kohei Matsuda, M. Nagata, S. Bhasin, Ville Yli-Mayry, N. Homma, Y. Mathieu, T. Graba, J. Danger\",\"doi\":\"10.23919/VLSIC.2017.8008502\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance.\",\"PeriodicalId\":176340,\"journal\":{\"name\":\"2017 Symposium on VLSI Circuits\",\"volume\":\"126 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2017.8008502\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2017.8008502","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor
An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
