采用四分之一速率三推测混合dfe接收机的28.05Gb/s收发器，在32nm CMOS中校准采样相位

2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI:10.23919/VLSIC.2017.8008527

G. Gangasani, J. Bulzacchelli, M. Wielgos, W. Kelly, Vivek Sharma, A. Prati, G. Cervelli, Daniele Gardellini, Matthew Baecher, M. Shannon, T. Beukema, Jon Garlett, H. H. Xu, T. Toifl, M. Meghelli, J. Ewen, D. Storaska

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引用次数: 2

摘要

本文提出了一种采用32nm SOI CMOS技术的28.05Gb/s收发器。接收机采用四分之一三重投机架构。介绍了适应分接权值、增益和采样相位不匹配的技术。在48dB损耗背板通道上演示了收发器在28.05Gb/s的无错误信号。在四端口配置中，28.05Gb/s的功耗为484mW/lane, FOM为0.36mW/Gb/s/dB。

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A 28.05Gb/s transceiver using quarter-rate triple-speculation hybrid-DFE receiver with calibrated sampling phases in 32nm CMOS

This paper presents a 28.05Gb/s transceiver in 32nm SOI CMOS technology. The receiver employs a quarterrate triple-speculation architecture. Techniques are introduced to adapt for mismatches in tap weights, gains and sampling phases. Error-free signaling at 28.05Gb/s is demonstrated with the transceiver over a 48dB loss backplane channel. In a four-port configuration, the power consumption at 28.05Gb/s is 484mW/lane, giving a FOM of 0.36mW/Gb/s/dB.

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2017 Symposium on VLSI Circuits

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