A 65nm CMOS I/Q RF power DAC with 24–42dB 3rd harmonic cancellation and up to 18dB mixed-signal filtering

Bonjern Yang, Eric Y. Chang, A. Niknejad, B. Nikolić, E. Alon
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引用次数: 2

Abstract

This paper presents an RF DAC transmitter (TX) with integrated, programmable harmonic cancellation as well as mixed-signal filtering at a peak power of 25.6dBm. The 65nm CMOS prototype uses device stacking and transformer combining and demonstrates 24dB to 42dB HD3 reduction across a frequency range of 0.7GHz to 2GHz, and up to 18dB of notching at a 40MHz offset.
65nm CMOS I/Q射频功率DAC,具有24-42dB三次谐波抵消和高达18dB混合信号滤波
本文介绍了一种射频DAC发射机(TX),它具有集成的、可编程的谐波消除和混合信号滤波,峰值功率为25.6dBm。65nm CMOS原型采用器件堆叠和变压器组合,在0.7GHz至2GHz的频率范围内实现了24dB至42dB的HD3降低,并在40MHz偏移量下实现了高达18dB的陷波。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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