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2017 Symposium on VLSI Circuits最新文献

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A battery-less 507nW SoC with integrated platform power manager and SiP interfaces 无电池507nW SoC，集成平台电源管理器和SiP接口
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008532
Farah B. Yahya, Christopher J. Lukas, J. Breiholz, Abhishek Roy, H. Patel, Ningxi Liu, Xing Chen, A. Kosari, Shuo Li, Divya Akella, Oluseyi A. Ayorinde, D. Wentzloff, B. Calhoun
{"title":"A battery-less 507nW SoC with integrated platform power manager and SiP interfaces","authors":"Farah B. Yahya, Christopher J. Lukas, J. Breiholz, Abhishek Roy, H. Patel, Ningxi Liu, Xing Chen, A. Kosari, Shuo Li, Divya Akella, Oluseyi A. Ayorinde, D. Wentzloff, B. Calhoun","doi":"10.23919/VLSIC.2017.8008532","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008532","url":null,"abstract":"A 507nW self-powered SoC is demonstrated for ultra-low power (ULP) internet-of-things (IoT) applications. The SoC includes ULP system-in-package (SiP) interfaces that enable its harmonious integration with a radio transmitter (TX) and a non-volatile memory (NVM). The energy harvesting platform power manager (EH-PPM) powers the SoC as well as off-chip components and is optimized for low quiescent power. It supplies the SoC with 0.5V, 1.0V, and 1.8V and can also power ULP sensors and the SiP components while running an example shipping-integrity tracking algorithm. A power monitor (PM) cold-boots the SoC from NVM and adapts the system's power consumption. The tight integration between the SoC's blocks enables sub-μW operation.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117252438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Chip-scale fluorescence imager for in vivo microscopic cancer detection 用于体内显微肿瘤检测的芯片级荧光成像仪
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008565
Efthymios P. Papageorgiou, B. Boser, M. Anwar
{"title":"Chip-scale fluorescence imager for in vivo microscopic cancer detection","authors":"Efthymios P. Papageorgiou, B. Boser, M. Anwar","doi":"10.23919/VLSIC.2017.8008565","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008565","url":null,"abstract":"Modern cancer treatment faces the pervasive challenge of identifying microscopic cancer foci in vivo, but no imaging device exists with the ability to identify these cells intraoperatively, where they can be removed. We introduce a novel CMOS sensor that identifies foci of less than 200 cancer cells labeled with fluorescent biomarkers in 50ms. The sensor's miniature size enables manipulation within a small, morphologically complex, tumor cavity. Recognizing that focusing optics traditionally used in fluorescence imagers present a barrier to miniaturization, we integrate stacked CMOS metal layers above each photodiode to form angle-selective gratings, rejecting background light and deblurring the image. A high-gain capacitive transimpedance amplifier based pixel with 8.2V/s per pW sensitivity and a dark current minimization circuit enables rapid detection of microscopic clusters of 100s of tumor cells with minimal error.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125351679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A −242-dB FOM and −71-dBc reference spur ring-VCO-based ultra-low-jitter switched-loop-filter PLL using a fast phase-error correction technique 采用快速相位误差校正技术的- 242 db FOM和- 71 dbc参考杂散环- vco超低抖动开关环滤波器锁相环
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008476
Taeho Seong, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi
{"title":"A −242-dB FOM and −71-dBc reference spur ring-VCO-based ultra-low-jitter switched-loop-filter PLL using a fast phase-error correction technique","authors":"Taeho Seong, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi","doi":"10.23919/VLSIC.2017.8008476","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008476","url":null,"abstract":"This work presents an ultra-low jitter, low-reference spur switched-loop-filter (SLF) PLL that uses a fast phase-error correction (FPEC) technique that emulates the phase-realignment mechanism of an injection-locked clock multiplier (ILCM). Despite a high multiplication factor (i.e., 64), the proposed SLF-PLL concurrently achieved ultra-low jitter and low reference spur. From the prototype that was fabricated using a 65-nm CMOS process, the RMS-jitter, the FOM, and the reference spur were measured as 378 fs, −242 dB, and −71 dBc, respectively.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125359908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 4.2mW 10MHz BW 74.4dB SNDR fourth-order CT DSM with second-order digital noise coupling utilizing an 8b SAR ADC 采用8b SAR ADC的4.2mW 10MHz BW 74.4dB SNDR四阶CT DSM与二阶数字噪声耦合
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008537
Il-Hoon Jang, M. Seo, Mi-Young Kim, Jae-Keun Lee, Seung-Yeob Baek, Sunwoo Kwon, Michael Choi, H. Ko, S. Ryu
{"title":"A 4.2mW 10MHz BW 74.4dB SNDR fourth-order CT DSM with second-order digital noise coupling utilizing an 8b SAR ADC","authors":"Il-Hoon Jang, M. Seo, Mi-Young Kim, Jae-Keun Lee, Seung-Yeob Baek, Sunwoo Kwon, Michael Choi, H. Ko, S. Ryu","doi":"10.23919/VLSIC.2017.8008537","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008537","url":null,"abstract":"A compact and low-power digital-domain noise coupling technique is proposed for higher-order CT DSM implementation, exploiting the architectural advantage of a SAR ADC and a simple digital filter. With an 8b SAR ADC and a second-order digital noise coupling filter, a prototype fourth-order DSM achieves 74.4dB SNDR for 10MHz BW with an OSR of 16 in a 28nm CMOS, showing an FoMs_dr of 174.5dB.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121509021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
3.37 μW/Ch modular scalable neural recording system with embedded lossless compression for dynamic power reduction 3.37 μW/Ch模块化可扩展神经记录系统，嵌入式无损压缩，用于动态降低功耗
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008468
Sung-Yun Park, Jihyun Cho, E. Yoon
{"title":"3.37 μW/Ch modular scalable neural recording system with embedded lossless compression for dynamic power reduction","authors":"Sung-Yun Park, Jihyun Cho, E. Yoon","doi":"10.23919/VLSIC.2017.8008468","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008468","url":null,"abstract":"We report a neural recording system with embedded lossless compression using spatiotemporal correlation and sparsity of neural signals to reduce dynamic power (Pd) dissipation for data transmission in high-density neural recording systems. We could successfully compress the data rate of neural signals by a factor of 5.35 (local field potential, LFP) and 10.54 (action potential, AP), respectively. Consequently we reduced Pd consumption by 89% while achieving the state-of-the-art recording performance of 3.37 μW/Ch, 5.18 μVrms input-referred noise, and 3.41NEF2Vdd.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115176604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Ultra-low power probabilistic IMT neurons for stochastic sampling machines 随机采样机的超低功耗概率IMT神经元
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIT.2017.7998148
M. Jerry, A. Parihar, B. Grisafe, A. Raychowdhury, S. Datta
{"title":"Ultra-low power probabilistic IMT neurons for stochastic sampling machines","authors":"M. Jerry, A. Parihar, B. Grisafe, A. Raychowdhury, S. Datta","doi":"10.23919/VLSIT.2017.7998148","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998148","url":null,"abstract":"Stochastic sampling machines (SSM) utilize neural sampling from probabilistic spiking neurons to escape local minima and prevent overfitting of training datasets [1]. This enables improved error rates compared to deterministic implementations, and, in turn, enables lower bit precision, decreased chip area, and reduced energy consumption. In this work, we experimentally demonstrate: (i) Insulator-to-Metal Phase Transition (IMT) neurons with record low peak operating power of 11.9μW at VDD=0.7V; (ii) the IMT in vanadium dioxide (VO2) provides a natural probabilistic hardware substrate for realizing a compact stochastic IMT neuron for SSMs; (iii) implementation of SSM for pattern recognition on MNIST database [2] using experimentally calibrated device modeling. These results are compared to a 22nm CMOS ASIC which shows stochastic IMT neuron based SSMs result in a 4.5x reduction in system power consumption.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123635783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A 1.2V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications 采用F-chip的1.2V 1.33Gb/s/pin 8Tb NAND闪存多芯片封装，适用于低功耗和高性能存储应用
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008479
Hyun-Jin Kim, Youngdon Choi, Jangwoo Lee, J. Byun, Seungwoo Yu, Daehoon Na, Jungjune Park, Kwangwon Kim, Anil Kavala, Youngmin Jo, Chang-Rae Kim, Sunghoon Kim, Nahyun Kim, Jaehwan Kim, Bong-Kil Jung, Y. Lee, Chanjin Park, Han-Sung Joo, Kisung Kim, Yu-Soo Choi, Pansuk Kwak, Hyeonggon Kim, Jeong-Don Ihm, D. Byeon, Jin-Yub Lee, Ki-Tae Park, K. Kyung
{"title":"A 1.2V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications","authors":"Hyun-Jin Kim, Youngdon Choi, Jangwoo Lee, J. Byun, Seungwoo Yu, Daehoon Na, Jungjune Park, Kwangwon Kim, Anil Kavala, Youngmin Jo, Chang-Rae Kim, Sunghoon Kim, Nahyun Kim, Jaehwan Kim, Bong-Kil Jung, Y. Lee, Chanjin Park, Han-Sung Joo, Kisung Kim, Yu-Soo Choi, Pansuk Kwak, Hyeonggon Kim, Jeong-Don Ihm, D. Byeon, Jin-Yub Lee, Ki-Tae Park, K. Kyung","doi":"10.23919/VLSIC.2017.8008479","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008479","url":null,"abstract":"A 1.2 V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package incorporating 16-die stacked 512-Gb NAND flash memories and F-Chip is presented. To meet the performance requirements of storage devices for higher capacity and faster data throughput, the 2nd generation F-Chip is developed. The F-Chip presents a dual bi-directional transceiver architecture including data retiming and training techniques to adaptively improve signal integrity. Besides, the F-Chip supports 1.2 V I/O for low power storage applications. This work, as a result, shows 33% improvement of eye-opening performances and 41% reduction of I/O power consumption compared to the previous generation.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"1020 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116458573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 16 nm FinFET 0.4 V inductor-less cellular receiver front-end with 10 mW ultra-low power and 0.31 mm2 ultra-small area for 5G system in sub-6 GHz band 一种16nm FinFET 0.4 V无电感蜂窝接收器前端，10 mW超低功耗，0.31 mm2超小面积，用于sub-6 GHz频段的5G系统
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008553
E. Yeh, An-Hsun Lo, Wen-Sheng Chen, Tsu-Jin Yeh, Mark Chen
{"title":"A 16 nm FinFET 0.4 V inductor-less cellular receiver front-end with 10 mW ultra-low power and 0.31 mm2 ultra-small area for 5G system in sub-6 GHz band","authors":"E. Yeh, An-Hsun Lo, Wen-Sheng Chen, Tsu-Jin Yeh, Mark Chen","doi":"10.23919/VLSIC.2017.8008553","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008553","url":null,"abstract":"This work presents an inductor-less 0.4 V cellular receiver (RX) front-end with an ultra-low power of 10 mW and an ultra-small area 0.31 mm2 in 16 nm FinFET technology, which enables massive receivers in a single chip for 10 Gb/s high throughput 5G system in sub-6 GHz band. The proposed inductor-less low-Vdd RX front-end consists of an LNA, passive mixers, LO generator and 20MHz bandwidth channel filters. By using the proposed current stabilization circuit in 0.4 V channel filter, the current variation with process corners is greatly reduced. This RX front-end can achieve a noise figure of 2.5dB, an in-band IIP3 of −6 dBm, a voltage gain of 35 dB at 2.1 GHz Band-I frequency. To the best of authors' knowledge, this work demonstrates the lowest power consumption with minimum chip area and a competitive performance under the lowest supply voltage of 0.4 V, compared with the prior arts.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130392113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An FFE TX with 3.8x eye improvement by automatic impedance adaptation for universal compatibility with arbitrary channel and RX impedances 通过自动阻抗适应，可与任意通道和RX阻抗通用兼容，使FFE TX具有3.8倍的视觉改善
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008547
Minsoo Choi, Sooeun Lee, Myungguk Lee, Jihoon Lee, J. Sim, Hong-June Park, Byungsub Kim
{"title":"An FFE TX with 3.8x eye improvement by automatic impedance adaptation for universal compatibility with arbitrary channel and RX impedances","authors":"Minsoo Choi, Sooeun Lee, Myungguk Lee, Jihoon Lee, J. Sim, Hong-June Park, Byungsub Kim","doi":"10.23919/VLSIC.2017.8008547","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008547","url":null,"abstract":"An FFE TX which automatically adapts impedance to arbitrary channel and RX impedances is proposed. Based on on-chip TDR monitoring, the TX impedance matching is adaptively relaxed without increasing reflection. In experiment, the proposed TX adapted to any combination of 35–75Ω channels and 30–200Ω RX impedances, achieving 3.8x eye improvement and the maximum data rate of 12Gb/s.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132004266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A scalable, highly-multiplexed delta-encoded digital feedback ECoG recording amplifier with common and differential-mode artifact suppression 具有共模和差模伪影抑制的可扩展、高复用增量编码数字反馈ECoG记录放大器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008470
W. A. Smith, J. Uehlin, S. Perlmutter, J. Rudell, V. Sathe
{"title":"A scalable, highly-multiplexed delta-encoded digital feedback ECoG recording amplifier with common and differential-mode artifact suppression","authors":"W. A. Smith, J. Uehlin, S. Perlmutter, J. Rudell, V. Sathe","doi":"10.23919/VLSIC.2017.8008470","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008470","url":null,"abstract":"We present a scalable, highly multiplexed CMOS electro-cortocography (ECoG) recording front-end capable of differential-mode and common-mode artifact suppression. The front-end digitally delta-encodes 8-bit data converters to achieve 14-bit resolution. A single, shared mixed-signal front-end is time-division multiplexed to 64 differential input channels; this reduces channel area by 10x compared to the state-of-the-art. A return-to-zero scheme effectively eliminates channel crosstalk. We present performance and in-vivo measurement results of a 65nm CMOS test-chip implementation of the proposed architecture.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129236022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
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