Hyun-Jin Kim, Youngdon Choi, Jangwoo Lee, J. Byun, Seungwoo Yu, Daehoon Na, Jungjune Park, Kwangwon Kim, Anil Kavala, Youngmin Jo, Chang-Rae Kim, Sunghoon Kim, Nahyun Kim, Jaehwan Kim, Bong-Kil Jung, Y. Lee, Chanjin Park, Han-Sung Joo, Kisung Kim, Yu-Soo Choi, Pansuk Kwak, Hyeonggon Kim, Jeong-Don Ihm, D. Byeon, Jin-Yub Lee, Ki-Tae Park, K. Kyung
{"title":"A 1.2V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications","authors":"Hyun-Jin Kim, Youngdon Choi, Jangwoo Lee, J. Byun, Seungwoo Yu, Daehoon Na, Jungjune Park, Kwangwon Kim, Anil Kavala, Youngmin Jo, Chang-Rae Kim, Sunghoon Kim, Nahyun Kim, Jaehwan Kim, Bong-Kil Jung, Y. Lee, Chanjin Park, Han-Sung Joo, Kisung Kim, Yu-Soo Choi, Pansuk Kwak, Hyeonggon Kim, Jeong-Don Ihm, D. Byeon, Jin-Yub Lee, Ki-Tae Park, K. Kyung","doi":"10.23919/VLSIC.2017.8008479","DOIUrl":null,"url":null,"abstract":"A 1.2 V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package incorporating 16-die stacked 512-Gb NAND flash memories and F-Chip is presented. To meet the performance requirements of storage devices for higher capacity and faster data throughput, the 2nd generation F-Chip is developed. The F-Chip presents a dual bi-directional transceiver architecture including data retiming and training techniques to adaptively improve signal integrity. Besides, the F-Chip supports 1.2 V I/O for low power storage applications. This work, as a result, shows 33% improvement of eye-opening performances and 41% reduction of I/O power consumption compared to the previous generation.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"1020 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2017.8008479","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
A 1.2 V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package incorporating 16-die stacked 512-Gb NAND flash memories and F-Chip is presented. To meet the performance requirements of storage devices for higher capacity and faster data throughput, the 2nd generation F-Chip is developed. The F-Chip presents a dual bi-directional transceiver architecture including data retiming and training techniques to adaptively improve signal integrity. Besides, the F-Chip supports 1.2 V I/O for low power storage applications. This work, as a result, shows 33% improvement of eye-opening performances and 41% reduction of I/O power consumption compared to the previous generation.
提出了一种包含16片堆叠512gb NAND闪存和F-Chip的1.2 V 1.33Gb/s/引脚8Tb NAND闪存多芯片封装方案。为了满足存储设备对更高容量和更快数据吞吐量的性能要求,开发了第二代F-Chip。F-Chip提出了一种双双向收发器架构,包括数据重定时和训练技术,以自适应地提高信号完整性。此外,F-Chip还支持1.2 V I/O,适用于低功耗存储应用。这项工作的结果是,与上一代相比,它的性能提高了33%,I/O功耗降低了41%。