A scalable, highly-multiplexed delta-encoded digital feedback ECoG recording amplifier with common and differential-mode artifact suppression

W. A. Smith, J. Uehlin, S. Perlmutter, J. Rudell, V. Sathe
{"title":"A scalable, highly-multiplexed delta-encoded digital feedback ECoG recording amplifier with common and differential-mode artifact suppression","authors":"W. A. Smith, J. Uehlin, S. Perlmutter, J. Rudell, V. Sathe","doi":"10.23919/VLSIC.2017.8008470","DOIUrl":null,"url":null,"abstract":"We present a scalable, highly multiplexed CMOS electro-cortocography (ECoG) recording front-end capable of differential-mode and common-mode artifact suppression. The front-end digitally delta-encodes 8-bit data converters to achieve 14-bit resolution. A single, shared mixed-signal front-end is time-division multiplexed to 64 differential input channels; this reduces channel area by 10x compared to the state-of-the-art. A return-to-zero scheme effectively eliminates channel crosstalk. We present performance and in-vivo measurement results of a 65nm CMOS test-chip implementation of the proposed architecture.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"31","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2017.8008470","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 31

Abstract

We present a scalable, highly multiplexed CMOS electro-cortocography (ECoG) recording front-end capable of differential-mode and common-mode artifact suppression. The front-end digitally delta-encodes 8-bit data converters to achieve 14-bit resolution. A single, shared mixed-signal front-end is time-division multiplexed to 64 differential input channels; this reduces channel area by 10x compared to the state-of-the-art. A return-to-zero scheme effectively eliminates channel crosstalk. We present performance and in-vivo measurement results of a 65nm CMOS test-chip implementation of the proposed architecture.
具有共模和差模伪影抑制的可扩展、高复用增量编码数字反馈ECoG记录放大器
我们提出了一种可扩展的,高复用的CMOS电皮层(ECoG)记录前端,能够抑制差模和共模伪影。前端对8位数据转换器进行数字增量编码,实现14位分辨率。单个共享混合信号前端被时分多路复用到64个差分输入通道;与最先进的技术相比,这减少了10倍的通道面积。归零方案有效地消除了信道串扰。我们给出了该架构的65nm CMOS测试芯片实现的性能和体内测量结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信