采用8b SAR ADC的4.2mW 10MHz BW 74.4dB SNDR四阶CT DSM与二阶数字噪声耦合

2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI:10.23919/VLSIC.2017.8008537

Il-Hoon Jang, M. Seo, Mi-Young Kim, Jae-Keun Lee, Seung-Yeob Baek, Sunwoo Kwon, Michael Choi, H. Ko, S. Ryu

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引用次数: 19

摘要

利用SAR ADC和简单数字滤波器的结构优势，提出了一种紧凑、低功耗的数字域噪声耦合技术，用于实现高阶CT DSM。采用8b SAR ADC和二阶数字噪声耦合滤波器，在28nm CMOS中，四阶DSM原型在10MHz BW下实现了74.4dB的SNDR, OSR为16，显示出174.5dB的FoMs_dr。

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A 4.2mW 10MHz BW 74.4dB SNDR fourth-order CT DSM with second-order digital noise coupling utilizing an 8b SAR ADC

A compact and low-power digital-domain noise coupling technique is proposed for higher-order CT DSM implementation, exploiting the architectural advantage of a SAR ADC and a simple digital filter. With an 8b SAR ADC and a second-order digital noise coupling filter, a prototype fourth-order DSM achieves 74.4dB SNDR for 10MHz BW with an OSR of 16 in a 28nm CMOS, showing an FoMs_dr of 174.5dB.

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2017 Symposium on VLSI Circuits

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