5Gb/s 7.1fJ/b/mm 8×多滴片上10mm数据链路,采用14nm FinFET CMOS SOI,电压0.5V

E. Sacco, P. Francese, M. Brändli, C. Menolfi, T. Morf, A. Cevrero, I. Ozkaya, M. Kossel, L. Kull, D. Luu, Hazar Yueksel, G. Gielen, T. Toifl
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引用次数: 4

摘要

我们报告了一个采用14nm FinFET CMOS SOI技术实现的5Gb/s数据链路,其中单个发射器(TX)将NRZ数据广播到分布在片上rc主导的10mm长的通道上的八个接收器(RXs)。TX包括一个全速率交流耦合2分接FIR驱动器和一个四分之一速率预驱动器。每个RX都配备了针对低功耗优化的新型决策门控1抽头推测DFE。RX架构是半速率,切片数据以四分之一速率解复用。可在片上提供PRBS发生器和检查器。通过以5Gb/s的速度传输PRBS31数据,验证操作正确,并在每次下降时同时接收无错误,水平边际>40% (BER<10−12)。在这个数据速率下,效率为7.1fJ/b/mm’,这是迄今为止公布的(据我们所知)多滴片上数据链路中性能最好的。TX和8台rx使用0.5 V电源,功耗分别为0.62和0.98mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 5Gb/s 7.1fJ/b/mm 8× multi-drop on-chip 10mm data link in 14nm FinFET CMOS SOI at 0.5V
We report a 5Gb/s data link implemented in 14nm FinFET CMOS SOI technology in which a single transmitter (TX) broadcasts NRZ data to eight receivers (RXs) distributed along an on-chip RC-dominated 10mm-long channel. The TX comprises a full-rate AC-coupled 2-tap FIR driver with a quarter-rate pre-driver. Each RX is equipped with a novel decision-gated 1-tap speculative DFE optimized for low-power. The RX architecture is half-rate and sliced data are de-multiplexed at quarter-rate. PRBS generator and checker are available on-chip. Correct operation was verified with PRBS31 data transmitted at 5Gb/s and concurrently received error-free at each drop with >40% horizontal margin (BER<10−12). At this data-rate the efficiency is 7.1fJ/b/mm' resulting in the best performance among multi-drop on-chip data links so far published (to the best of our knowledge). The TX and eight RXs are running on a 0.5 V power supply and consume 0.62 and 0.98mW' respectively.
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